In our talks with Intel researchers, we learned that the second goal of Tera Scale Computing is to get an SRAM die stacked on top of a multi-core Tera Scale die for massive amount of bandwidth, and keeping the chip size in order, or more importantly - skipping the increase of the package size, which could limit the final working clock of the product.
In the car industry, "welding" is used to join the chassis and the engine. In IT terms, we cannot figure a better term for joining two silicons together in holy matrimony, till death or electro-migration tear them apart. Romantic, isn't it?
The ingenious part is what kind of connection will be used for this wedding of silicon - classical ball arrangement, that is used on to combine silicon and packaging of today, just like Conroe, Kentsfield or just about any of your regular FC-PGA chips out there. Both silicons will be englazed in same amount of protective plastics, and tucked beneath the IHS (Integrated Heat Spreader).
So, without further ado, here's a wafer that features insane amount of SRAM memory and has Polaris (80-core) stuck next to it. In the near future, these two would be cut and placed one above the other.