[NextGen_Gamer]

Originally Posted by Malikus

I want this card

Nice monster ... one thing to ati - PLEASE DON'T CHANGE THE COLOR - BLACK IS AWESOME

I totally agree about the black PCB. It looks dead sexy.

Originally Posted by tutu69

sorry, but u live the wrong dream...my dear; my feelings tells me otherwise, but goddammit,,,the signals are way to weak to comprehend my own thoughts.

intel pulls nothing out of their head and only nv knows the magically route; god bless the NVONE! or 3dfx, or my beloved old WOLFENSTEIN,,,so where is carmack, where is the software thats belongs to all that uberpower of hardware?

only time will tell!

I just thought I would let you know that John Carmarck already stated that the Xbox 360 would be the lead platform for his next engine and game. The PC version will be a port of the Xbox 360 one. Also, just in case you forgot, the Xbox 360 uses an ATI-developed GPU (R500 or "Xenos"). Sooo...

Originally Posted by ImmortalZ

You guys don't understand.

They NEED the bridge chip, side port or not. How else are you going to split the x16 into 2 x8s for each chip? The so called bridge chip is actually a PCI Express Switch - it handles two devices on a single x16 port - or in other words, splits the x16 into 2 x8s.

You simply can't split an imaginary 16 pins into 2 groups of 8 and be done with it. Also, the bridge chip on this iteration looks much smaller than the one used in the 3870X2 and since the part no.s are edited out, we don't know what has changed.

It might be that the PLX no longer handles inter-chip communication - just 2 chips -> motherboard. The Crossfire sideport or memory sharing might be happening - we just can't tell.

There is only one Crossfire connector because scaling above 3 cores is non-existant, even with DX10's expanded limits for forward rendering.

You are right. Even with an integrated CrossFire Sideport or HyperTransport link or whatever, ATI would still need a bridge chip to split the PCI-E lanes between the two GPUs. Think of it like this (only pay attention to the red text, nothing else):

GPU 0 <------------> GPU 1
^ ............................... ^
¦ ................................ ¦
¦ ................................ ¦
¦-----> PLX Bridge <-----¦
............... ^
............... ¦
............... ¦
... PCI Express Interface

So, R700 could still have a shared memory pool between the two GPUs. But even if it doesn't, it should still offer higher CrossFire efficiency scaling versus a pair of Radeon HD 4870 cards in CrossFire.

[Ekklesis]

Actually it has PLX chip for splitting the x16 bus offered by the mainboard cause that's that PLX chips are doing and the direct connection between the chips is through the memory and that means that the speed between them will increase from 8GB and something wich was the link speed on 3870X2 to the speed of DDR 512bit(actually 256bit up and down) wich will gonna be over 100GB.Rest assure that the limitations that appeared between chips on 3870X2 board will be just a bad memory...

[aaapasser]

The CrossFire Sideport is a new feature of the RV770 architecture that isn't in use on the RV770 at all. In future, single-card, multi-GPU solutions (*cough* R700) this interface will be used to communicate between adjacent GPUs - in theory allowing for better scaling with CrossFire. We'll be able to test this shortly as AMD is quickly readying its dual-GPU RV770 card under the R700 codename.



http://anandtech.com/video/showdoc.aspx?i=3341&p=9

[neurra]

is it me seeing that the board has no caps at all or it's just that?

[power666]

Originally Posted by ImmortalZ

They NEED the bridge chip, side port or not. How else are you going to split the x16 into 2 x8s for each chip? The so called bridge chip is actually a PCI Express Switch - it handles two devices on a single x16 port - or in other words, splits the x16 into 2 x8s.

The same way two Opterons can communicate with the IO chip even though its only connected to one of the two sockets. The catch is that the additional hop incurs a latency penalty. PCI-E is a high latency bus but that is a non-issue since data can be prefetched with high accuracy. Having a shared pool of memory could potientially reduce the amount of traffic across the Crossfire sideband bus via only sending the data that is necessary.

Data switching and forwarding via the Crossfire sideband bus shouldn't be that difficult to implement in hardware.

Originally Posted by ImmortalZ

There is only one Crossfire connector because scaling above 3 cores is non-existant, even with DX10's expanded limits for forward rendering.

This is mainly a software issue but in the hands of game developers. I suspect that their is a away for significant performance gains via a multithreaded multi-GPU. The problem is letting game developers catch up to the graphics hardwre.

[ImmortalZ]

Originally Posted by power666

This is mainly a software issue but in the hands of game developers. I suspect that their is a away for significant performance gains via a multithreaded multi-GPU. The problem is letting game developers catch up to the graphics hardwre.

I remember reading somewhere that this was a limitation of the DX10 API and not game engines themselves.

[Kappa33]

black pcb!