[VRNews]

AMD's next generation architecture, codenamed Bulldozer, will feature a multi-threading system, Xbitlabs reports. However, AMD claims that Bulldozer's multi-threading is different from the simultaneous multi-threading (SMT) available with Intel's HyperThreading. More details next page.


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AMD's next generation CPU features multi-threading

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[NextGen_Gamer]

VR-Zone should have waited a little while before posting this news, as X-bit Labs has since updated their article:

UPDATE: AMD has contacted X-bit labs claiming that it has not announced any simultaneous multi-threading technologies for Bulldozer processors. Still, there are other multi-threading implementations that may still be supported.

This doesn't necessarily mean that the "Bulldozer" architecture will not have some form of SMT in it, only that AMD is not confirming that it does at this point in time.

[haylui]

to know more about AMD next gen architecture through patent registered by AMD

Patent based research regarding AMD's future MPUs

[power666]

Originally Posted by haylui

to know more about AMD next gen architecture through patent registered by AMD

Patent based research regarding AMD's future MPUs

What is weird is that there are two integer clusters, complete with their own individual register sets. I highly doubt that AMD is trying to do anything like the old DEC Alpha by mirroring the register file to quick access to each pool of execution resources. The DEC Alpha did that with the FPU which allowed time to synchronize the register sets. Integer operations tend to be very fast so I doubt that there is enough time for synchronization between the clusters.

Alternatively, the integer unit clusters could be for their own dedicated thread where the FPU is shared between them. That would make far more sense in the design. This would work well in a system that implements multithreading by time division multiplexing: each stage in the processor pipeline is occupied by a different thread. The advantage here is that a thread does not feel the impact of a pipeline stall for a mispredicted branch. The disadvantage is that the per thread performance drops.

AMD could also be trying their hand at out-of-order instruction retirement. This is one of the big features in Sun's (cancelled?) Rock processor. By cramming in a work on a per thread basis in the pipeline, there should be enough time for the scheduler to know if it has to wait for dependencies for retiring instructions.

The one thing that strikes me is that AMD maybe trying to create a chip capable of running multiple instruction sets. The two big ones would be x86 of course and their Radeon GPU's. The more graphics friendly code would be able to function without the legacy bloat the x86 ISA provides. Further more, AMD can provide just-in-time compilers that produce micro-ops directly for that chip's architecture. That would cut out the decode stages in the processor pipeline for specific non-x86 threads.

[eEnzo0]

I quote from a site wich implies Bulldozer patent

In my eyes it was a smart move to mention SMT - just to be able to deny it . However, this is still speculation.

Instead we saw the term "Cluster-based Multi-threading" (also known as clustered multi-threading, CMT) already years ago in an AMD presentation. If you look at Chuck Moore's slide below, you see, that SMT is the least admirable multi-threading variant to AMD. So far they were underway in the CMP part of this diagram and it just seems logical to move to much greener CMT area from there - even more since they explicitly state a 50% area investment for 80% throughput gain.