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Discussing the AMD-ATI deal...Parts 1&2 bbmf Jul 26th, 06, 07:20 PM #256 (permalink)

AMD EVP Henri Richard

This is Part I of two-part interview.
***
Q: If you look at the figures that have been given, the ATI acquisition is being funded by the US$2.5 billion loan, plus cash and cash equivalents and short-term investment balances of approximately US$3.0 billion. That’s total funding of US$5.5 billion. That covers a basic acquisition valued at US$5.4 billion. I think the suspicion, here, among the general public and among your shareholders, might be that AMD is taking too much of a risk with this acquisition, that you’re betting the farm on a deal that might be very questionable.
A: I don’t think we have the feeling that we’re betting the farm. We’re very enthusiastic about this transaction because we think that it’s a necessary step in our quest to break the monopoly. Having the opportunity to innovate, in an equal way, at the platform level, more so than we could in the past, is certainly part of our strategy. As well, we have always been recognizing that there’s a certain amount of balance needed in system performance, between all the various components. Now we have two of the key components, two of the key technologies, the CPU and the GPU, and we’re going to be able to continue to move forward in terms of innovation to balance out, for the best interests of our end users and customers, these two key technologies. That’s something we couldn’t do before. So there’s no trepidation from our side, and certainly not from the management team, in terms of, “Is this a transaction we can’t afford?” If we had felt that way, we wouldn’t have done it.
Now it’s clear that recently the market has been taking a beating, and not only our stock. That said, to a certain degree, we’ll pass. We’ve always known this was a marathon. You don’t go and break a monopoly the size of Intel in a few short quarters, and Hector [AMD President and CEO Hector Ruiz] is keeping his eyes focused on the long-term strategy, which is to be able to offer two alternatives to the industry, and I think this takes us one more step in that direction. In fact, for the first time this positions AMD in the marketplace with solutions that Intel doesn’t have, because one of the very exciting aspects of the ATI product portfolio is the technology they have in the digital consumer space. So not only are we becoming a more potent PC player, and to a certain degree we’re doubling down on the investment for the PC marketplace, we’re also now adding a certain number of very key technologies in the consumer-electronics space, both in handsets and digital TV, and that’s pretty exciting. ATI’s got a very large market share in cell phones, and ATI is also a very important player in digital TV.
Q: So, obviously, part of the acquisition strategy is to leverage ATI’s technology in both those segments?
A: Well, frankly, these are segments where we’re not present, so for us they are new markets, and clearly, with the deep knowledge and respect that ATI has in those markets, it opens up new opportunities for AMD by essentially using some of our IP and getting some of it applied to some of those particular segments.
Q: So are you saying that handsets are a new segment for AMD?
A: Through this acquisition, absolutely. We had absolutely no presence in that market. Previously we had a presence in the handset market through Spansion and our flash business, but after the separation from Spansion, we basically had lost the relationship or the reason to establish a relationship in handsets.
Q: So what exactly is it that you hope to gain from ATI, in term of handsets?
A: Well, if you think about the evolution of the handset market, there’s an increasing body of evidence that new products, like the UMPC and portable devices that are neither a small notebook nor a smartphone, seem to be one of the hot topics of conversation these days, particularly here in Taiwan, and I think that for us, re-establishing a very strong partnership, through this ATI acquisition, with companies such as Nokia or Motorola, is an interesting element. If you start to think about the future of mobile computing, there’s now the possibility that some of those key industry market makers might decide to enter that space.
Q: Of course, digital TV might well become a feature of the handset market.
A: Well, I look at digital TV from a different angle. If you think about it, if you have a flat-panel TV, it doesn’t take much to turn it into a media center, so there again there could be some opportunities, as we leverage the very very deep and wide relationship that ATI has established in that marketplace, to listen to customers and see in what direction we could innovate to service their needs.
As you know, with our AMD Live! initiative, we took a very different approach to that of Intel. We’re not trying to force everyone into a single bottle. We’re trying to listen to customers and what they think they really need in the living room, and frankly, if it was the case that some large flat-panel manufacturers decided they should add PC functionality to their flat panels, that could be an interesting opportunity for AMD or the new company.
As well, I was talking with some customers today, and there are a lot of new ideas, where the phone could become more linked in the home, becoming a portable display, for example, so there are a lot of things going on, particularly as VoIP becomes more pervasive. In this kind of scenario, by default, phones will have some sort of IP based connection with your home network, and that in itself presents a lot of interesting opportunities for us.
Q: In the past AMD has always been closely associated with the name Nvidia, and it’s always been assumed that AMD has a very positive relationship with Nvidia, if not an actual partnership. We’ve heard terms such as SNAP, the strategic Nvidia-AMD partnership. What are the implications for your relationship with Nvidia, now that AMD has made this move to acquire a company that has always been a competitor with Nvidia?
A: Well, first, we have to remember the principle under which we’re going to continue to operate our joint business, which is one of open platforms and open standards. There’s nothing in our strategy that, unlike our competitor, is going to be aimed at hurting or impairing the ability of other folk to innovate on our platform. As such, I expect our relationship with Nvidia to continue to be one that is both a partnership and a strategic relationship because again we respect the innovation that Nvidia brings to the marketplace, and we certainly want them to feel that if they invest some of that capability for innovation on the AMD platform, there’s going to be a just return on that investment. So those principles that have helped build AMD are not going to change.
Q: So can we continue to anticipate AMD based motherboards that carry Nvidia graphics and Nvidia core logic?
A: I surely hope so, absolutely. I come as you know from a background at IBM, and one of the principles I learned there, and I think this is very important, is that if internal divisions are to remain competitive, you should not shield them from external competition. I think that’s one very important aspect of competition. So, although I would expect that our internal chipset division would provide us with very high quality, very high performance chipsets, I know for a fact that artificially shielding them from external competition would probably be bad business practice.
From time to time it may happen that we will have the best chipset for a particular application, and from time to time it may happen that Nvidia has the best chipset. And if that’s the case, there’s absolutely no reason why they shouldn’t reap the benefit of their innovation. We’re certainly going to maintain an open platform strategy, so that they can innovate on the AMD platform. Also, unlike the competition, I don’t foresee putting in place artificial marketing barriers to force our customers to make certain choices that are not necessarily good for their business.
Q: In the same context, AMD has always had a strong relationship with VIA Technologies. SiS and several other companies could probably be mentioned as well. Certainly VIA has always been regarded as a key provider of core logic for AMD, so do you have any comments on AMD’s future relationships with these third-party providers?
A: Well, all that I’ve just said about Nvidia would also be true for VIA, SiS and any other partner. It’s interesting to note that those three companies have been providing chipsets for the Intel eco-system for years, and I think that everyone would agree with me that working under the Intel umbrella is a lot more difficult than working with AMD. So these companies have been able to produce Intel based chipsets for years and finding a way to survive and thrive in that environment, so I don’t see why they wouldn’t be able to do it in the AMD eco-system.
Again, I can’t make comments for them. Some of them may decide that instead of making a broad offering, they’re going to focus on specific segments. I’m sure they’ll be looking at their strategies. But across the board, we’re going to maintain a very open platform and an open-standard approach to partnership with those three companies.
Q: Can you say what you hope to gain from the acquisition in terms of some specific components and functionality; for example, standalone graphics processors, an integrated graphics capability, gaming platforms and system-on-chip (SoC) solutions?
A: From time to time, over the past few years, we were in certain situations where a customer would have an idea, or would propose a level of collaboration or integration between the various components – for example, a chipset integrated with a CPU – and although we have great quality partnerships in the industry, issues can always arise. That’s not necessarily having an opposite view on a particular solution, but barriers can get in the way of implementing the most efficient solutions, simply because different companies have different priorities at different times. So one of the things that the ATI acquisition is going to allow us do, now that we have all the components of the puzzle, is listen to customers and really figure out how we can bring them innovation that is really meaningful to their business and that will allow them to differentiate and extend their business.
I think that this lack of differentiation, and this lack of expansion of their business might well be what has been hurting the industry the most, mainly because, again, our competitor has a tendency to want to normalize everything, rather than allow differentiation. So clearly we expect to continue to push the envelope on GPUs and provide ever increasing performance and quality and visualization of graphics. We believe there are opportunities to bring very high quality integrated graphics solutions to the marketplace, and I think that it’s particularly important to have a high quality cost-competitive solution in integrated UMA chipsets and gaming platforms for sure.
AMD has always been near and dear to the hearts of gamers. We can now think about innovating at that level, probably with our 4x4 enthusiast platforms. You’ll see some interesting and potential development around some of the IP that came with the ATI acquisition, and so forth. ATI has a relationship with Microsoft around the Xbox 360, and there are some interesting things there, I’m sure, for the future. There’s a vast array of opportunities for us to go and innovate and figure out how to balance performance and cost for the best interests of the end user. Basically, that means innovating without the artificial barriers that exist when you have separate companies, across the various elements.
In the long run, you can debate whether it’s at 45 nanometers or 32 nanometers or 22 nanometers, but at some point we’re going to have on-die a transistor budget that could probably support a further level of integration. In a multicore system on a chip, perhaps the CPU and GPU could be on the same die, for example. That’s not for the short-term. That requires a lot of R&D and development, but it’s clearly a possibility. That is of course something that a lot of customers will be asking us about, and that we’ll be starting to think about.
As you know, we’ve also just announced our Torrenza initiative, which is a multi-socket open architecture. I haven’t looked yet at what this could mean in terms of some of the IP that comes with the ATI acquisition, but clearly we are moving as quickly as we can in trying to offer this open-platform, open-socket, architecture, potentially licensing Coherent HyperTransport. Who knows what’s coming with all the talent and all the IP that’s part of the ATI acquisition? Maybe there are opportunities there for us to accelerate the Torrenza initiative and do some interesting things with some partners.
Q: How about systems-on-chip, as such, which would imply not only a processor and graphics capability but also memory, and so on.
A: Again there, we’re going to go back to the UMPC type of space. This is a very interesting space. With the 50x15 initiative, we’re very very close to all those new types of devices that require a system-on-chip capability, whether they’re for the ultra-mobility space, whether they’re for the ultra-low-cost space, and there again we believe that by having the complete set of tools and building blocks, we’ll be able to bring a level of innovation at the complete system level that we couldn’t when we were just AMD as a CPU company. It’s too early for me to disclose anything. We’ve got to go and do some hard work now, but certainly we know there are a lot of great opportunities to take some of the great technology that ATI develops for markets that are adjacent to the PC market and see if by combining some of those technologies with what we know about the PC market, we can create a new paradigm or a new level of performance at power and cost envelopes that have not been achieved so far.
Q: Could you concretize a little more how that might work out in terms of specific devices. You mentioned 50x15, for example.
A: Well, if you look at the context of 50x15, and if you look today, for example, at a very high-end multimedia phone, one could argue that one approach is a UMPC device that could provide Internet access to 50% of the population in 2015. To achieve that, you could start from a PC and try to cost reduce it, reduce its size down to that level of device, or you could start from a multimedia phone and try to up-size it, slightly, to arrive at the level of functionality you want in that device.
That’s one of the areas, clearly, where we’re going to ask our engineers to go think about how they can take the best technologies from both parties and innovate and provide a device that will attract new customers.
***

sa: http://www.digitimes.com/news/a20060725VL204.html
 
Last edited by bbmf; Jul 26th, 06 at 07:33 PM..
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Discussing the AMD-ATI deal...Continued bbmf Jul 26th, 06, 07:31 PM #257 (permalink)
This is Part II of a two-part interview.
***
Q: You mentioned previously the possibility of taking a flat-panel display and making it the center of a multimedia center for the home, and so on. That probably implies a set-top box (STB) or a PVR or DVR type of device. Does AMD have its eye on that particular segment, the set-top box?
A: Well, again because of our open approach with AMD Live! and the fact that we're not trying to coerce the eco-system into going to the PC to access every piece of content, we've been able to get pretty good support from large players in the STB and PVR spaces. Motorola is one of them. STMicro is another. So I think there are opportunities for bringing x86-type technology to some of these markets. Now, with ATI, we have a great graphics rendering capability, a very good understanding of the entire video pipeline, so I think that will position us, even more, as a valid trusted partner for some of those large players in the consumer-electronics space, all of whom are very nervous about how Intel is approaching that environment. In other words, when they see how the PC market functions, they don't necessarily want to import that business model into the consumer-electronics market. We aim to provide them with an alternative that will probably make them more comfortable with the competitive environment.
Q: Do you expect to gain any capability in integrated PCIe, through the deal with ATI?
A: We've been looking at integrated PCIe for a while, There are pros and cons to that. I wouldn't rule it out, but I have no specific comment on that.
I'm sure that when you start to take great GPU engineers, and great glue logic, chipset and CPU engineers, and you put them in the same room and say, "Forget all the old artificial boundaries between those three elements. Focus instead on what you could do to make the PC platform a better platform," I think there are going to be some very interesting brain storming sessions. I don't know what exactly is going to come out of them, but I'm looking forward to those brain storming sessions.
It's fair to say that, if we thought that this was just a plug-in of the existing business, with absolutely no synergies and no opportunity for new and relevant innovation, I'm not sure that we would have been as excited as we are about the deal. I think a lot of work has been done already. The engineers have come up with some interesting ideas, but I'm not prepared to talk too much about them today.
Q: Obviously the acquisition does have implications for the fabrication of ATI's products. ATI's products are not based, like AMD's, on SOI technology. So in practice, how will things work from a manufacturing point of view?
A: In practice, we're not going to change anything. ATI is going to continue to rely on a fabless model. We want to nurture the great relationship that exists, here in Taiwan, with TSMC. And you're right, because they're on bulk wafers, and we're on SOI, even if there was a good reason for us to go and think about doing things differently, it's not practical in any short period of time. As I mentioned, one day it will make sense to put a GPU and CPU on the same die. In that case, of course, they would have to be manufactured on the same process.
But right now, AMD's manufacturing strategy is focused on increasing rapidly, as per plan, our CPU capacity, so we don't want to do anything to disrupt that. And then ATI has a very successful model, working very closely with TSMC, and we don't want to disrupt that either. So we'll be both a fab and a fabless company, and we are looking forward to getting the best of both those worlds.
Q: So over the next year, possibly two years, going into 2008, let's say, the large majority of ATI chips will still be made by TSMC, while AMD continues to use your existing capacity?
A: That's correct. AMD chips will be manufactured at Fab 30, Fab 36, Fab 38 and then Chartered. Right now, AMD's relationship with Chartered is doing very well, but that extra capacity that we have through Chartered is really focused on our x86 processor manufacturing.
Q: But I assume that at some point AMD will try to move ATI products to AMD's process.
A: It could make sense. We've always been a believer that SOI has some intrinsic advantages, and I have to think that some way out in the future, if that's the case, why not? But recognizing that GPU technology and cycles are different from CPU cycles, we don't want to do anything to impose upon what is a very successful business today, with any preconceived idea of what to do and what not to do. Now again, this is in the context of separate products. But if you accept the concept that at some point it would make sense to integrate the different products on the same die, then by default we would be using the same process, an AMD process.
Q: So it looks as though if you want to pursue highly integrated designs, you'll have to try to implement ATI parts on AMD's process.
A: At some point.
Q: Intel claims to dominate the integrated graphics market, or it claims to dominate the graphics market, per se, by virtue of its integrated graphics. So I assume that a central plank of your strategy was acquiring ATI in order to compete with Intel at that level.
A: Sure. I think that Intel has been putting together a set of strategies to try to close their eco-system and make it difficult for not only AMD to compete against their CPUs but for other companies to compete against their chipset strategies. As a new company we're still as dedicated as AMD was alone to fighting this monopoly and breaking this monopoly. Being able to go and challenge some of the strategies that the competition has put together around the chipset will help us in that quest.
But the fact is that Intel has never really had high quality graphics, and it's certainly one of their weakest technology areas. So one could argue that with the ATI acquisition, we now have one of the best portfolios in the mobile space, as well as in power management and UMA graphics.
Q: You're absolutely confident, then, at this stage, that you can now start to compete with Intel in terms of quality of integrated graphics?
A: Oh I think we are definitely capable of offering higher quality graphics than they can, in the integrated space.
Q: And obviously here we're talking more about a consumer segment than specialized gaming platforms?
A: Right.
Q: So have you, at AMD, looked carefully at what particular percentage or slice of the processor market you could hope to gain by offering integrated graphics?
A: Well, our objectives are not changing. We've said clearly that our target is to get a 30% revenue share of the industry by 2008. That remains our target. Based on the second quarter of this year, we seem to be well on track to reach that in the server space. We've got good momentum as well in the desktop space. We are a fairly new entrant in the mobile space, and I think that particularly in the mobility space, the ATI acquisition is going to help us accelerate in the market.
If you look at ATI's market share, they have a very strong presence on both the AMD and Intel platform. I think the ATI brand is very well recognized, as a provider of premium UMA graphics solutions for both the Intel and the AMD platforms. Another thing I could mention that's interesting for us is the depth and quality of industry relationships that ATI brings to the company, including relationships with OEMs that don't do business with AMD. So I see all these elements as opportunities for us to accelerate our penetration of the mobile market and to continue our aggressive new-customer acquisition strategy.
Q: How are you defining the mobile market?
A: I'm talking about laptops, notebooks of course.
Q: In the set-top box space, do you see the ATI acquisition as potentially giving you an edge, in terms of product integration, particularly in integrated graphics, in any potentially competitive situation with Intel?
A: Well, you know, Intel is not particularly present in the set-top box business, so I'm not sure what they're going to do. I'm not going to speculate on their strategies. We think that AMD and ATI as a combined company can be the premier partner, not only for PC manufacturers but also for consumer-electronics companies. I think the consumer-electronics companies have had a great relationship with ATI. And we're bringing a very solid x86 expertise that may or may not be of interest to them, depending on which segment of the consumer-electronics space they're in.
Q: I mention set-top boxes in the context of Intel because I've always had the suspicion that they have one eye on being able to transform a low-cost, very compact box into an STB. And that once they have some I/O extender technology attached to a PC, in, say, one of the BTX form factors, it would be an easy move for them to leverage that kind of configuration for the STB market.
A: You're absolutely right, and that's why they're not getting a lot of support because the people that are in the STB business are not particularly keen on trying to help Intel enable that, because Intel would then have a displacement strategy, not a complementary strategy, whereas we are trying to be complementary, not displacing people.
But I still think that the complexity of putting all these solutions together, makes it, from my perspective, not something for the very short-term. I think it will come, but there is a lot of work to be done, particularly in terms of software integration in the living room, to make the promise of having these various technologies interact with each other a reality, and to make it a reality in a bug-free environment for the end user. But it's an interesting challenge and one that the new company will be able to tackle better than AMD alone.
Q: I see that the acquisition is subject to ATI-shareholder final approval. What confidence do you have that ATI shareholders will approve the deal? Have you in fact tried to assess what their response will be?
A: I think we feel very good about the fact that this deal is going to go through. Both AMD and ATI are not competitors. There's really not a lot of regulatory exposure, from that perspective. Both boards have been very supportive. I think we're making a fair offer. And I believe that once we get a chance to explain why we're doing this, people will understand that this is going to be good for the industry. So I'd be shocked if we weren't able to gather the support of the ATI shareholders and, perhaps more importantly, the support of ATI employees. I think people will get enthused, and I think that in many ways this is a new chapter for our industry. If you think about it, this is a pretty deep and far-reaching announcement.
Q: We can expect to have closure on the deal by the fourth quarter, as I understand it.
A: We expect, barring any unforeseen issues, that the deal should be final sometime in the fourth quarter. And we'll enter 2007 with an industry that will never look quite the same.
Q: If you do not, in fact, finally acquire ATI, what do you think ATI's state of health will be in the market? Do you think they'll have difficulty in surviving? Do you think they require this acquisition by AMD to survive?
A: No, I think ATI has a choice to be a successful independent graphics and chipset company. But obviously, as we started to talk with each other and look at the possibilities for the combined company in the marketplace, both managements came to the conclusion that the acquisition would be the best route forward for both companies. ATI hasn't done this out of any short-term necessity or even long-term necessity.
Perhaps the only element that could have been on the horizon is that at some point in time, the sheer budget of transistors available implies that at some level the GPU technology and CPU technology would share the same die. If you look at it from that perspective, it's not a matter of if but of when. And then you could argue whether that would be in this decade or next decade, but I'm sure there was something of that thinking in ATI's management. But this is a very good company that is performing well. It has a lot of very happy customers, and we're very glad that we could convince them that joining forces with AMD would be a big plus for both our employees and shareholders, and perhaps most importantly for our customers. It's our customers who kept telling us that, one way or the other, we should do something like this.
***
sa: http://www.digitimes.com/systems/a20060726VL203.html
 
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AMD Demonstrates Enthusiast 4x4 Platform bbmf Jul 26th, 06, 07:57 PM #258 (permalink)
AMD shows off enthusiast platform performing "mega-tasking"
AMD has been all over the news in the past week, first with its massive price cuts and second with its merger with ATI. In a bid to steal Intel’s quad-core limelight, AMD held a demonstration of its previously announced 4x4 enthusiast platform. The demo placed great emphasis on "mega-tasking," showing the 4x4 system running various multitasking scenarios. Some scenarios included playing games while a video was being encoded in the background or multiple CPU bound applications running simultaneously. AMD’s demo systems were powered by two unnamed dual-core Athlon 64 FX processors and compared to an Athlon 64 FX-62 equipped system.
During the event, AMD stated end-users should be able to pickup a pair of 4x4 compatible processors for under $1000. Previously, AMD had claimed that the 4x4 platform would be limited to the FX series processors only, and currently all FX series CPUs are priced at least $500. No specifications were available on bundled 4x4 Athlon 64 FX processors.
AMD 4x4 systems will be NUMA compatible allowing each processor access to its own pair of 240-pin DDR2 memory slots. However, memory capacity appears to be handicapped on 4x4 systems with a maximum of 2GB per processor. There was no mention of Athlon 64 X2 compatibility in 4x4 systems or details on the motherboards.

sa: http://www.dailytech.com/article.aspx?newsid=3509&ref=y
 
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ATI To Release X1650 To Compete With G73 bbmf Jul 26th, 06, 08:18 PM #259 (permalink)
Since nVidia released Geforce 7600 family (G73) in March, its corresponding rival Radeon X1600 was facing a strong enemy with lower cost and better performance, forcing ATi to recall a weakened R520 version Radeon X1800GTO (R520LE) for the level. In long term, ATi is going to release new Radeon X1650 family.
Radeon X1650 is composed by RV560, RV530 and RV535 chipset, where RV560 is correspond to the top model 1650XT. They are manufactured by TSMC with 80nm process, featured 8 Pixel Shader Pipelines, 24 Pixel Shader Processors (12 for RV530), 128Bit memory controller with 1.4GHz DDR support, 600MHz clock speed and build-in Compositing CrossFire Engine. It is no more master/salve card for CrossFire. Expected to be available in October, its price is set between $149 and $199.
After the launch of Radeon X1650XT, source hinted that Radeon X1600XT and Radeon X1600Pro would be renamed as Radeon X1650Pro and Radeon X1300XT with no any change in specification. Besides, the 80nm version of RV530 is available in October, codenamed RV535 and manufactured by TSMC. With a lower cost, ATi would definitely become more compatible. Radeon X1650 Pro is expected in $99 to $119, while Radeon X1300XT is expected in $79 to $99.

sa: http://www.digit-life.com/news.html?06/52/89
 
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bbmf Jul 26th, 06, 08:30 PM #260 (permalink)

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Panasonic, NEC, TI join forces on future mobile phones bbmf Jul 28th, 06, 01:50 PM #261 (permalink)

NEC President Kaoru Yano (left) and Matsushita President Fumio Ohtsubo close the deal.
Matsushita and NEC Corp. are teaming with Texas Instruments to form a mobile phone joint venture that will share R&D activities. The Japanese companies want to use the deal to become global wireless players.
The joint venture, dubbed Adcore-Tech Co. Ltd., includes a communications platform development effort in which all three partners will participate. A second handset development effort will inlude only Matsushita subisidiary Panasonic Mobile Communications and NEC.
Adcore will generally focus on developing a communications platform for 3G, 3.5G, 3.9G and beyond, The JV will be launched in August with a ¥12 billion yen (about $104 million) investment. Matsushita and NEC will each hold a 44-percent share, with TI holding the remaining 12 percent.
The Japanese partners are seeking a new framework for their the mobile phone business that includes development of baseband chips for 3G and beyond along with a common handset development environment backed by the Open Mobile Linux consortium established in June.
In joining forces with TI, the two companies—dominant in Japan but minor players in the world market—want to establish a beachhead in the global market.
The partners will license their technologies to Adcore to develop communications chips. The resulting technology will be licensed to each member's semiconductor unit. Matsushita's Semiconductor Co., NEC Electronics Corp. and TI will sell the chips to handset vendors.
Matsushita and NEC also plan to shrink their overseas mobile phone operations and focus on the domestic market to improve profitability.
The partners said they are aiming to supply 20 percent of wideband-CDMA communications chips to the global market by 2008. "TI has accumulated 2.5G technology. Together with NEC's and Matsushita's's technology, quite competitive chips will be developed," predicted NEC President Kaoru Yano.
Toshiyuki Kawasaki, president of Texas Intruments Japan, said the JV focuses on communications modems, and does not include TI's OMAP wireless technology.
Adcore will initially have a staff of 180 engineers. TI has not decided how many engineers it will contribute to the joint venture.

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MRAM...for the uninitiated bbmf Jul 28th, 06, 02:46 PM #262 (permalink)
MRAM (magnetic random access memory) technology, based on the use of magnetic tunnel junctions (MTJs) as memory elements, is a potentially fast nonvolatile memory technology with very high write endurance. This paper is an overview of MRAM design considerations. Topics covered include MRAM fundamentals, array architecture, several associated design studies, and scaling challenges. In addition, a 16-Mb MRAM demonstration vehicle is described, and performance results are presented.

This is an abridged version of the article. Full text may be viewed by following link at bottom of post.
Introduction
MRAM may be a cost-effective solution for long-term data retention and rapid on/off applications such as mobile handheld and general consumer electronic systems. In such cases MRAM may effectively replace a battery and SRAM (static random access memory) and/or flash memory to provide fast, low-power, nonvolatile storage. In large-system applications requiring a reduction in system start-up time (boot time) and the protection of memory contents in the event of sudden unexpected power-down events, MRAM may serve as a replacement for various combinations of SRAM, DRAM (dynamic random access memory), and flash memory components.
MRAM fundamentals
MTJ device structure
Figure 1 is an illustrative drawing (not to scale) of the fundamental MTJ device structure used for binary storage; it consists of two ferromagnetic layers separated by a thin tunnel dielectric [1, 2]. The lower layer is “fixed,” implying that its magnetic orientation cannot be changed during operation, whereas the magnetic orientation of the upper, “free” layer can be changed by the application of a sufficiently large magnetic field. The MTJ is shaped to fit into a rectangular box and is patterned in various shapes within the box as a circle, an oval, an ellipse, or some sort of re-entrant “Saturn” shape [3]. The long axis of the free layer is oriented parallel to the uniaxial anisotropy magnetic orientation of the fixed layer, resulting in a magnetic orientation of the free layer in two stable states: in the same direction as the fixed layer (parallel) or in the opposite direction (anti-parallel). While conceptually simple, the fixed and free layers are in fact multilayer structures constructed to achieve the desired read, write, and thermal stability characteristics.

When a small bias voltage is applied between the fixed and free layers, a tunneling current flows through the thin intervening dielectric layer. The magnitude of the current depends on the state of the free layer, with the parallel state having a higher current. The current–voltage characteristic of the device can be modeled as a nonlinear resistor, with the resistance being dependent upon the state of the free layer. The fractional change in the effective resistance is known as the magnetoresistance (MR), which is defined by
R1 = R0(1 + MR).
where R1 is the effective resistance of the anti-parallel state and R0 is that of the parallel state. At this stage in the development of MRAM technology, MR values for integrated devices are typically in the range of 30–50%, while new materials under development provide MR values in excess of 100% [4].
Figure 2 llustrates the percentage of change in the effective resistance (relative to the low-resistance, parallel state) as a function of applied magnetic field. The applied field is assumed to be parallel to the long axis of the MTJ. The MR for this particular example is approximately 65%. Note that the switching between the two states is hysteretic; that is, the transition from the high- to the low-resistance state (1 to 0) does not occur at the same applied magnetic field as in the reverse order (0 to 1). This hysteretic behavior allows the device to be used as a memory element.

The MTJ structure is integrated into the interconnect portion of an otherwise typical CMOS integrated circuit structure. The CMOS devices allow the integration of circuits to address, read, and write the MTJ memory elements.
MTJ read operation
The MTJ device is read by measuring the effective resistance of the structure, which is a function of the state of the MTJ free layer. This can be achieved by applying a voltage and sensing the current (current sensing) or by applying a current and sensing the voltage (voltage sensing). In either case, the sensed parameter (assumed to be current in the following) is compared to a reference value to determine the state of the device.
The fractional value change in effective resistance or MR is not constant but rather decreases with increasing read voltage. Therefore, the relative signal or fractional difference between the data and reference currents decreases with increasing voltage. However, the absolute signal or absolute difference between the data and reference currents vanishes as the voltage approaches zero. Both relative and absolute signals are critical for a robust, high-performance design. Therefore there exists an optimum value of the read voltage, which appears to be approximately 200 to 300 mV.
Reference method
The reference value must be designed to compensate for process-related variations in MTJ parameters (R0 and MR) and for environmental variations such as voltage and temperature. Three general methods are known for generating the reference value: the twin cell, reference cell and self-referenced methods [5–8]. Current sensing is described in the following examples, although the methods apply to voltage sensing as well.
In the twin cell method, two MTJs are used to store one data bit. The true and complementary MTJs are always written to opposite states. The current associated with the true MTJ is sensed and compared with that of the complementary MTJ to determine the value of the stored data. Use of the twin cell method results in the maximum possible raw signal. However, it has the obvious density disadvantage of requiring two MTJs per bit. In addition, it is sensitive to parameter mismatch between the true and complementary MTJs.
In the reference cell method, the current associated with the data MTJ is sensed and compared with that associated with one or more reference MTJs, which are preprogrammed to known states. If a single reference cell of known state is used, the reference cell current must be multiplied by a certain factor in order to position the reference midway between the 0 and 1 state currents. In another approach, two reference cells are used and are preprogrammed to opposite states. The average of the two reference cell currents is used as the reference. The use of the reference cell method results in only half the raw signal of the twin cell approach, but the MRAM that can be fabricated using this method is much denser, since a reference cell can be shared among many cells. It is also sensitive to parameter mismatch between the data and reference MTJs.
In the self-referenced method, the current associated with the MTJ is sensed and the value is momentarily stored. The same MTJ is then written to a known state and the current is sensed a second time. The original value of the current is compared with the known state current, again multiplied by a certain factor to position it midway between the 0 and 1 state currents. Alternately, the second current value is also momentarily stored, and the MTJ is written to the opposite known state and sensed a third time, permitting the original current to be compared with the average of the 0 and 1 state currents. Assuming that the read cycle is not allowed to disturb the stored data, the original state of the MTJ must then be restored. The self-referenced method utilizes the same raw signal as the reference cell method, requires no chip area for reference cells, and is insensitive to MTJ parameter mismatch, since MTJ is referenced solely to itself. Unfortunately, the repeated write and sense cycles add considerably to the read access, cycle times, and read active power.
Because of its attractive combination of high density, high performance, low power, and high degree of symmetry, the current-sensing two-reference-cell design appears to be the most popular approach. With this method, the raw signal must be sufficiently large to compensate for parameter mismatch between the data and reference cells as well as offsets within the sense amplifier (SA). This requirement places strict requirements on the MR, MTJ parameter matching, and design of the SA.
MTJ write operation
Figure 3 illustrates the MRAM write operation. The selected MTJ, shown in red, is situated between the selected word line (WL) and the selected bit line (BL), both shown in green, which are orthogonal to each other. During the write, currents (blue arrows) are forced along the selected WL and the selected BL, creating magnetic fields in the vicinity of these wires. The vector sum of the fields at the selected MTJ must be sufficient to switch its state. However, the field generated by the WL or BL alone must be small enough that it never switches the state of the so-called half-selected MTJs that lie along the selected WL and BL.

The process is designed so that the word lines and bit lines are as close as possible to the MTJs for good magnetic coupling to the MTJs. Nonetheless, currents of the order of 5 mA are typically required to switch the state of an MTJ. These currents are considered large by integrated circuit standards and create a variety of challenges for write circuit design. Further, the associated IR drops along the lines limit their allowable lengths, limiting the maximum number of cells in a memory array.
The pulse widths of the WL and BL current pulses are typically approximately equal to or less than 10 ns. However, the two pulses are typically offset by a few ns, with the WL pulse beginning first, so that the free layer can be switched to its new state in a controlled manner.
The magnetic field experienced by WL or BL half-selected MTJs is perpendicular to the wire that generates the field. Further, the field applied to the fully selected MTJ points in a third, somewhat diagonal direction. The hysteresis loop of Figure 2 is insufficient to fully describe these situations, since it is limited to fields in one direction only (along the long axis). The astroid plot, illustrated in Figure 4, describes the switching of the free layer in response to both field strength and direction.

The x- and y-axes represent the x and y components of the magnetic field applied to the MTJ. In this figure, the long axis of the MTJ and the WL are assumed to be horizontal and the BL to be vertical. Since the WL field applied to the MTJ is perpendicular to and proportional to the WL current, the y component of the field is proportional to the WL current. Similarly, the x component of the field is proportional to the BL current.
The astroid plot is interpreted in the following manner. If the applied field begins at the origin (no applied field), moves to a point to the right of the y-axis and the diamond-shaped region, or astroid, and returns to the origin, the free layer will point to the right (data state 1). Similarly, if the applied field begins at the origin, moves to a point to the left of the y-axis and the astroid, and returns to the origin, the free layer will point to the left (data state 0). If the applied field remains inside the astroid, the state of the MTJ remains unchanged.
The fully selected MTJ experiences both x and y field components, placing it in the first or second quadrant of the figure depending on the data state to be written. Since the polarity of the x field component or BL current determines the written data state, the BL write circuitry must support a bidirectional current. The y field component is independent of the data state to be written, simplifying the design of the WL write circuitry because bidirectional currents are not required. In order to write successfully, the fully selected field points must always lie outside the astroid.
As indicated in Figure 4, WL half-selected MTJs experience a y field component only, whereas BL half-selected MTJs experience an x field component only. The polarity of the field experienced by a BL half-selected MTJ depends on the state being written to the fully selected MTJ. To avoid half-select disturbs (data loss between an MTJ being written and read), the half-select field points must always lie inside the astroid.
Write margin
Write margin is the ability to reliably write the selected MTJ without disturbing other bits. Write margin requires that the fully selected fields always lie outside the astroid, while the half-selected fields lie within the astroid. Several additional mechanisms degrade the write margin, as described below.
In addition to the half-select field described above, the two WL half-selected MTJs immediately adjacent to the fully selected MTJ experience a small x component field because of the adjacent BL current. Similarly, the two BL half-selected MTJs immediately adjacent to the fully selected MTJ experience a small y component field because of the adjacent WL current. The magnitude of these stray fields depends on the design of the memory cell and is typically less than 10% of the corresponding BL or WL field. Nonetheless, these stray fields further degrade the write margin. The stray field problem becomes more significant as the cell size and hence the distance to the adjacent WL and BL are reduced.
The astroid shown in Figure 4(a) is hypothetical. The shape and size of the astroid are dependent upon the shape, size, and other properties of the MTJ. Correspondingly, the shape and size of each MTJ within a chip vary because of local variations in shape, size, and other properties. The resulting statistical spread of the astroid further degrades the write margin. The write margin challenge is further exacerbated by the finite chance that MTJs operated close to the astroid boundary may undergo undesired thermally activated switching over a vanishingly small potential barrier from one data state to the other [9].
In addition, the applied field varies with variations in circuit parameters (FET parameters, wiring resistance, and supply voltage). The resulting variations in the position of the full and half-select field points [see Figure 4(b)] on the astroid plot degrade the write margin still further. It is the goal of the write circuit design to limit these variations and to compensate for the temperature dependence of the astroid.
Toggle mode
In response to the write margin difficulties associated with the conventional MTJ device, a more complex, “toggle-mode” MTJ device and switching method have been developed [10, 11]. Figure 5 illustrates the toggle-mode MTJ device structure. The structure is similar to that of the conventional MTJ except that the free layer consists of two weakly anti-parallel coupled ferromagnetic layers. In addition, the long axis of the structure lies at approximately 45 degrees with respect to the WL as opposed to being parallel to the WL. The read operation is essentially unchanged, with the magnetic orientation of the lower free layer determining the effective resistance of the structure.

Whereas the conventional MTJ is written directly into one state or the other depending on the polarity of the BL current, the toggle-mode MTJ toggles its state when exposed to a similar WL and BL current pulse sequence. As illustrated in Figure 6, the dipoles of the free layer rotate slightly in the direction of the applied field, and essentially follow the applied field as it rotates during the WL and BL current pulse sequence. At the end of the sequence, the free-layer dipoles have rotated 180 degrees from the initial state, regardless of the initial state. The criterion for a successful toggle is that the applied field must trace a path in the applied field plane that encloses a particular point in the plane, referred to as the “spin-flop” point.

Unlike a conventional MTJ, a toggle-mode MTJ is largely insensitive to half-select disturbs, regardless of WL and BL field strength, since such disturbs do not trace a path that encloses the spin-flop point. In addition, since the free layer has no net magnetic moment, the field experienced by a particular device is insensitive to the state of adjacent devices. This advantage is of particular importance as cell size and hence the distance to the adjacent devices are reduced. A final advantage of the toggle-mode MTJ is that only one BL write current direction must be supported, simplifying the design of the write circuits.
Because of the toggle nature of the device, the device must be read at the start of the write cycle. The device is then toggled if its current state does not match that of the incoming write data. Although the read can be performed concurrently with preparations for the WL and BL write pulse sequence, the required read represents a write-performance disadvantage compared with that of a conventional MTJ.
Array architecture
There exist two basic architectures for constructing an MRAM array—the cross-point (“XPT”) architecture and the one-transistor, one-MTJ (“1T1MTJ”) architecture [12], as illustrated respectively in Figures 7 and 8.

In the XPT architecture, the MTJs lie at the intersection of the WLs and BLs, which connect directly to the fixed and free layers (or vice versa). This arrangement allows for a considerable packing density. Since no contact is made to the silicon within the cell, it is possible to stack such arrays, thus further increasing MRAM density. In addition, it might be possible to place peripheral circuits under the array, increasing the density even further.
However, the XPT architecture involves several significant design challenges. Each MTJ introduces a resistance through which write current may be lost. The only effective way to limit this loss is to increase the effective resistance of the MTJ, which in turn reduces the absolute value of the signal during the read operation. Further, during the read operation, there is no device within the cell to assist in selecting the cell. As a result, current from other cells along the BL interferes with the sensing operation. The result of these effects, described later in greater detail, is very poor read performance.
In the 1T1MTJ array architecture, each MTJ is connected in series with an n-type FET, or n-FET. The n-FET, the gate of which is the read word line (RWL), is used to select the cell for the read operation. The write word line (WWL) runs directly below but does not actually contact the MTJ. The RWL and WWL run parallel to each other and perpendicular to the BL, which contacts the free layer of the MTJ. The source of the n-FET is grounded, whereas the drain connects to the fixed layer of the MTJ via a thin local interconnect layer. This layer and the dielectric below it are relatively thin in order to ensure good magnetic coupling from the WWL to the MTJ.
The density of the 1T1MTJ array architecture is less than that of the XPT array architecture for several reasons. The 1T1MTJ cell must include sufficient space for the contact extending down from the thin local interconnect layer, which is typically adjacent to the MTJ since the WWL is directly below the MTJ. The cell size may also be limited by the size of the n-FET and its associated source/drain contacts. In contrast to the XPT architecture, it would be difficult to stack multiple layers of 1T1MTJ arrays, since each cell must make contact with the silicon below it. Similarly, it would not be possible to place the peripheral circuits below the array because the silicon is utilized by the n-FETs of the cells.
Electrically, the 1T1MTJ array architecture has several advantages. During write operation all RWLs are low, eliminating the possibility of losing write current through the MTJs. As a result, the effective resistance of an MTJ may be much lower and the absolute read signal therefore much higher than in the XPT array architecture. Further, only the selected RWL is driven high during a read operation, preventing currents from other MTJs on the BL from interfering with the sensing operation. For these reasons, the read performance of the 1T1MTJ array architecture is far superior to that of the XPT.
For a variety of reasons including its superior read performance, the 1T1MTJ appears to be preferable.

sa: http://www.research.ibm.com/journal/rd/501/maffitt.html
 
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Parallel processor firm enhances core for HD video bbmf Jul 28th, 06, 04:15 PM #263 (permalink)
PACT XPP Technologies AG, a developer of a reconfigurable highly parallel processor, has redesigned its technology to produce the XPP-III version of its architecture and claimed that performance, for the first time, allows high definition video decoding without additional hardware accelerators.
On the original version of the XPP architecture, released in October 2000, PACT included 128 processors and an FPGA-like array of interconnectivity. Pact (Munich, Germany) added a package of video processor configurations and multi-standard video codecs for porting to its XPP-II parallel processor in January 2005.
The XPP-III is a software programmable standalone processor platform for signal processing applications. It combines a coarse-grained reconfigurable array with a sequential architecture for the control-flow code. Although the main target application is video, the XPP-III is a general purpose processor which can be used in other application fields such as wireless baseband processing, the company said.
Pact claimed it had overcome some of the development and programming issues that have dogged other multiprocessor architectures with the provision of a complete tool chain, including an ANSI C compiler, and accompanying application libraries. This would allow software developers to concentrate on application writing while making use of flexible hardware, Pact said. The company said that the architecture is well suited to compute heavy consumer applications such as video processing for high-definition television, for HDTV set-top boxes, and Blu-ray and HD-DVD decoders as well as mobile applications.
The company plans to bring the architecture to market as licensable intellectual property for customers working on system-on-chips. In addition, Pact plans to offer chips for either high performance or mobile applications. The SMeXPP-3H for high performance and the SMeXPP-3M for mobile would become available in 2007 in volume, the company said.
In addition, Pact provides software modules for decoding MPEG4 ASP, H.264, and VC-1 and AES encryption and decryption. Software libraries also comprise software building blocks for customers who want to port their own applications to XPP-III.

sa: http://www.embedded.com/showArticle....leID=190900275
 
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Samsung to release 4GB flash drive for Vista... bbmf Jul 28th, 06, 04:25 PM #264 (permalink)
Korean electronics giant Samsung is gearing up to release a 4GB flash drive specifically designed to boost the performance of PCs running Windows Vista, due to be released early next year.
The resource hungry Vista is said to be a big consumer of memory and the Samsung flash drive will be used to launch applications by caching applications held on hard drive using a feature of Vista called ReadyBoost, which moves regularly used applications and data to flash memory.
While hard drive caching using RAM takes place as matter of course when running applications on Windows and other operating systems, the difference with the Samsung flash drive, which is due for release in the fourth quarter, is that it will not lose the cached data when the computer is turned off.
According to Samsung, typical Vista users will see significant performance increases when using the secondary flash drive.

sa: http://www.itwire.com.au/content/view/5118/53/
 
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Samsung Announces 8GB NAND Flash Memory bbmf Jul 28th, 06, 05:07 PM #265 (permalink)
Samsung Electronics Co., Ltd., today announced that it has begun mass producing an 8 GB NAND flash memory device, providing a much larger and more affordable storage density for consumer and mobile applications such as mobile phones, MP3 players and gaming consoles.
The high-density MLC memory is being produced with 60-nanometer (nm) process technology, the smallest used today. Samsung’s 8 GB NAND flash memory, developed in September 2004, is the fifth consecutive Samsung NAND flash memory to follow the New Memory Growth Model of double density growth every 12 months, a pattern conceived by Dr. Chang Gyu Hwang, president and CEO of Samsung Electronics Semiconductor Business.
The 8 GB NAND which can store 2000 MP3 files or 225 minutes of DVD-quality video is expected to be available in the third quarter of 2006. Samsung plans to further utilize its 8 GB NAND flash memory chip in Samsung’s high-density MLC NAND, called moviNAND, to produce a 2GB-level market solution.

sa: http://tech.moneycontrol.com/news/sa...ry/2181/india/
 
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NVIDIA SLI Power: Integrated & Discrete GPU's Together bbmf Jul 29th, 06, 02:26 PM #266 (permalink)
NVIDIA is working on combining an integrated and discrete GPU that switch seamlessly between power savings and performance.
This SLI is not combining graphics card for increased performance, but offering ultimate flexibility for notebook users.
High end models of Sony's current SZ series laptops already use dual graphics cards, an NVIDIA GeForce Go 7400 and Intel GMA 950. While there is a neat little external switch to change GPU's, it is nothing close to seamless and requires a reboot. Enter: SLI Power
SLI Power is the current tag line for a new technology NVIDIA is developing. Along the same lines as the Sony model, there will be both integrated and discrete NVIDIA graphics processors. Through complicated hardware logic and of course clock gating to cut power off to unused devices, NVIDIA plans to be able to seamlessly switch between integrated and discrete GPU's with no reboot needed.
Obviously this is easier said than done and the feature is still being developed. We hear that the software interface is being rather difficult, getting Windows to switch video device drivers on a whim and all. There is no word on when this may be completed, but we wouldn't be surprised to see this around Vista time.

sa: http://www.laptoplogic.com/news/deta...hardware.co.uk
 
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Wi-Fi in Your Handset... bbmf Jul 31st, 06, 09:15 AM #267 (permalink)
What if, instead of burning up minutes on your cellphone plan, you could make free or cheap calls over the wireless networks that allow Internet access in many coffee shops, airports and homes?
New phones coming on the market will allow just that.
Instead of relying on standard cellphone networks, the phones will make use of the anarchic global patchwork of so-called Wi-Fi hotspots. Other models will be able to switch easily between the two modes.
The phones, while a potential money-saver for consumers, could cause big problems for cellphone companies. They have invested billions in their nationwide networks of cell towers, and they could find that customers are bypassing them in favor of Wi-Fi connections. The struggling Bell operating companies could also suffer if the new phones accelerate the trend toward cheap Internet-based calling, reducing the need for a standard phone line in homes with wireless networks.
The spottiness of wireless Internet coverage means that for now, the phones will be more of a supplement to, rather than a replacement for, standard cellphone service. But dozens of American cities and towns are either building or considering wide-area wireless networks that would allow Wi-Fi phones to connect and make free or cheap calls.
“It’s a phone that looks, feels and acts like a cell phone, but it actually operates over the Wi-Fi network,” said Steve Howe, vice president of voice for EarthLink, which is building networks in Philadelphia and Anaheim, Calif.
Later this year it plans to introduce Wi-Fi phone service that Mr. Howe said could cost a fifth as much as traditional cell service.

sa: http://www.nytimes.com/2006/07/29/te...221&ei=5087%0A
 
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ATi R600 May Consume up to 200W Out of Box...nm OC bbmf Jul 31st, 06, 09:39 AM #268 (permalink)
ACCORDING TO PC WATCH, the next round of GPUs are going to be really smoking, not because they are fast, but because they suck power like it is going out of style.
If you read the article, you will see the damage that will be done to the world's petroleum reserves.
The short story is this, G80 form Nvidia is looking to suck down 175W on a 90nm process, probably a bit less on 80nm. R600 from ATI is looking to take about 200W in 80nm, and less if they pull off a shrink to 65nm.
Either way, this is simply too much. The current 100+W is borderline insane, and adding half again to it is just silly, speed is OK, but I think we have just passed the point of being ludicrous. When you are at more than twice the power of the CPU, it is time to hit yourself on the head with the same high velocity cluestick that AMD and Intel have already experienced

sa: http://theinquirer.net/default.aspx?article=33343
 
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Mozilla Thunderbird 2.0 Alpha bbmf Jul 31st, 06, 10:12 AM #269 (permalink)
Mozilla Corp. on Thursday gave users a first look at the next version of its Thunderbird e-mail client by releasing an alpha of v. 2.0.
Thunderbird 2.0 Alpha 1, which can be downloaded in Windows, Linux, and Mac OS X editions, is suitable for developers only, Mozilla said on its Web site, although there are no actual barriers that block others from trying the software.
"[It] is being made available for testing purposes only," Mozilla stated on the site. "Current users of Mozilla Thunderbird 1.5.0.x should not use Thunderbird 2 Alpha 1."
According to Mozilla's roadmap for Thunderbird 2.0, the alpha will be followed by a beta in late August, one or more release candidates in the fall, and a final in "late fall 2006."
Among the new features being tested in the client are message tagging, enhanced mail notification alerts, updates to the program's extension model, and a "Conversations" view mode (similar to the grouping used in Google's Gmail).
Also on Thursday, Mozilla released Thunderbird 1.5.0.5, a stability and security update that patched 12 flaws, including one judged "critical" by the company. Current users of Thunderbird 1.5.x will be notified of the update automatically; others can download the client from the Mozilla site.

Thunderbird 2.0 Alpha 1 can be downloaded from here.

SA: http://news.yahoo.com/s/cmp/20060729/tc_cmp/191504704
 
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"Crystal Illusion Screen" Creating More Dynamic Image Expression bbmf Aug 2nd, 06, 07:46 AM #270 (permalink)

DNP’ s "Crystal Illusion Screen" was awarded the Gold prize for the Display Component of the year at the Society for Information Display (SID) 2006, the world’s largest display related academic gathering, held at San Francisco, CA from June 4 to June 9. The "Crystal Illusion Screen" was highly praised as an unparalleled front projection type transparent screen with the projector positioned in front of the screen, and for the unique manufacturing process capitalizing on liquid crystal material coating technology.
Crystal Illusion Screen" is a transparent projection screen that is coated with special liquid crystal materials on the surface of the film. As the system efficiently reflects light only from projector images, it is possible to clearly display those images even in bright settings.
DNP has utilized the "SoundVu" flat panel speaker technology developed by New Transducers Limited (NXT) of Huntingdon, UK, and with development and manufacturing cooperation from Authentic Ltd., an NXT licensee, has added an audio input jack to directly link sound vibrations to the screen, creating an in-built speaker to produce sound directly from the screen itself.
In addition to the visual impact of images appearing on a transparent screen, as audio is generated throughout the entire screen, it is possible to pick up the sound on a 360 degree plain, facilitating a radical, attention grabbing form of image expression.
As the screen is transparent it is possible to use a projector without any loss to the design balance or image of the display space. Apart from the colorless transparent screen, DNP also stocks smoked type screens, which rein in external light, along with brown, blue and light blue tinted screens, making it possible to select a screen to match the environment and mood of the display setting.
As there is no need for an external speaker it is possible to maintain a compact display setting.
Any commercially available projector can be used with no restrictions on manufacturer or type.

sa: http://www.dnp.co.jp/eng/news/2006/060801.html
 
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