PACT XPP Technologies AG, a developer of a reconfigurable highly parallel processor, has redesigned its technology to produce the XPP-III version of its architecture and claimed that performance, for the first time, allows high definition video decoding without additional hardware accelerators.
On the original version of the XPP architecture, released in October 2000, PACT included 128 processors and an FPGA-like array of interconnectivity. Pact (Munich, Germany) added a package of video processor configurations and multi-standard video codecs for porting to its XPP-II parallel processor in January 2005.
The XPP-III is a software programmable standalone processor platform for signal processing applications. It combines a coarse-grained reconfigurable array with a sequential architecture for the control-flow code. Although the main target application is video, the XPP-III is a general purpose processor which can be used in other application fields such as wireless baseband processing, the company said.
Pact claimed it had overcome some of the development and programming issues that have dogged other multiprocessor architectures with the provision of a complete tool chain, including an ANSI C compiler, and accompanying application libraries. This would allow software developers to concentrate on application writing while making use of flexible hardware, Pact said. The company said that the architecture is well suited to compute heavy consumer applications such as video processing for high-definition television, for HDTV set-top boxes, and Blu-ray and HD-DVD decoders as well as mobile applications.
The company plans to bring the architecture to market as licensable intellectual property for customers working on system-on-chips. In addition, Pact plans to offer chips for either high performance or mobile applications. The SMeXPP-3H for high performance and the SMeXPP-3M for mobile would become available in 2007 in volume, the company said.
In addition, Pact provides software modules for decoding MPEG4 ASP, H.264, and VC-1 and AES encryption and decryption. Software libraries also comprise software building blocks for customers who want to port their own applications to XPP-III.
The XPP-III provides greater bandwidth for streaming data and sequential performance than DSPs, the company said. And, in comparison with FPGAs, the coarse-grained XPP dataflow array is an order of magnitude more area and power efficient and provides fast on-the-fly reconfiguration. And, unlike ASSP and FPGA-based systems, all components are programmable in C and the XPP-III does not need the support of additional of-the-shelf microprocessors, the company said.
C-code is compiled with the ANSI C-compiler (FNC-CC) for those tasks which have been selected for the sequential units (Function-PAEs). Dataflow type code sections for the XPP dataflow array are integrated using APIs and library functions. If required, dataflow functions for the array can be compiled with the XPP vectorizing C compiler (XPP-VC).
Pact also supplies a profiling tool to locate potential bottlenecks in the code, which may be resolved either by restructuring the program or by function calls to optimized assembler routines. The program can be simulated and debugged with cycle accuracy.
As a measure of performance Pact claimed that the XPP-III can process any kind of video decoder up to high definition resolution. An XPP core with 40 ALUs, 16 RAM programmable elements and 8 Function-PAEs implemented in 90-nm CMOS and achieving 350-MHz clock frequency would be able to execute H.264 main profile at 1920 by 1088 resolution including digital rights management from encrypted input, de-interlacing and picture enhancement.
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