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If you're a benchmark industry insider, you'll hardly find better person to talk to than Oliver Baltuch, currently serving as President of Futuremark Corporation. This engineer earned his spot in the industry while working for National Semiconductor, Vadem, SMSC, NVIDIA, Netcell and Chartered Semiconductor Corporation. Over the last few years, he's been helping benchmark maker Futuremark reinvent itself from a small enthusiast company, founded in Espoo, Finland, into a corporate powerhouse. Oliver is located in Futuremark's Silicon Valley office, in a lovely small city of Saratoga, CA.

Oliver likes to spend his free time exploring new areas.
With the upcoming release of next-generation 3DMark® Vantage, we felt this was quite a good reason to have an interview, so without further adieu, we give you Ollie.

TG Daily: Ollie, Futuremark had a very exciting 2007 with the launch of YouGamers.com and PCMark® Vantage. We're barely starting 2008 and you've already announced another project, Futuremark Games Studio. Could you tell us more about your current projects and how many fronts are you battling right now?
Oliver: Hi Theo, both of these are related to our renewed strategy which calls for more aggressive growth. We are operating on three new and different business areas: Internet (YouGamers.com), PC and perhaps also mobile (Futuremark Games Studio) and mobile/handheld/embedded benchmarks and demos with our new Content Creation Tool Chain (CCTC).
TGDaily: How large is the Futuremark operation as such and by how many people have you expanded in 2007? What is your plan for employment in 2008?
Oliver: At the end of 2007, we were 68 people. We actually doubled our headcount within the last two years. Right now, we're at a pretty good size for all the things we've got on our plates right now…
TG Daily: When it comes to YouGamers.com, the site has existed for over half a year now, so how satisfied are you with the growth of the site?
Oliver: We've put in a lot of effort to bring up YouGamers.com, to offer something unique to the gamers that no other site in the world offers. Regarding the amount of investment, we're very satisfied with the amount of users and traffic we've been able to grow. I think we're now within world's top 20 gaming web sites and our intention is to grow much bigger.
TG Daily: With your tradition in benchmarking, is Futuremark Gaming Studios going to build on that and create games that have advanced benchmarking tools inside, or do you want to separate the two as much as possible?
Oliver: Futuremark Games Studio is still pretty new. Right now the team is focusing on creating an amazing game play experience with breathtaking visuals that add to the game play. Our benchmarking team is still engaged in creating professional benchmarks (PCMark® and 3DMark®) that engage the consumer while being must-have tools that are relevant for benchmarking professionals (IT Managers, Journalists, Heavy Duty Overclockers) and consumers.
TG Daily: We would like to hear your personal opinion of how do you see impact of physics itself in the future of gaming?
Oliver: OK, personally I love the thought of Physics in Gaming as long as it adds to the game play experience. All the major games today involve some type of physics from flying mud in rally racing, to the arc of bullets in sniper modes. Depending on game genre that can mean better water, gravity, collisions etc…it can also add dramatically to the look of a game with clouds of dust or steam obscuring your escape from a large monster's claw in space.
One of returning tests in 3DMark is of course, never-ending Battle for Proxycon. This time around, space battle is one of epic proportions...
TGDaily: Let's turn back to the core business, benchmarking - Futuremark is a known player in that arena with the renowned 3DMark® and PCMark® series of benchmarks. How do you see benchmarking evolving in future?
Oliver: PC hardware and software is constantly evolving, making the PC's we use not only faster, but, adding tremendously to features and functionality. We are working with the finest engineers in the PC industry to define the next set of benchmarks that will include the ability to test that new hardware and software that was only dreamed about a couple of years ago. As a PC enthusiast with an engineering degree myself, I can hardly wait to see what new inventions will be coming.
TG Daily: With PCMark Vantage, Futuremark started with an interesting concept of paying for benchmarking, with PayPal being used for the simplified version. What are the reactions from your users?
Oliver: We had a good response to the PayPal, it made it much more convenient for our customers to purchase the software and I'm really glad that our service team in Finland was able to integrate the new functionality into our store. From the very start, serious benchmarkers have purchased the Advanced Editions as well as OEM's and IT Managers have purchased the Professional Editions. With PayPal, a whole new generation has access to our software.
TG Daily: Do you plan to continue this business model with 3DMarkVantage, which is an immensely popular benchmark?
Oliver: Yes. The new model we started with PCMark® Vantage was to have a trial version for no cost and then a Basic Edition which could be used over and over for less than 5 Euros (less than the price of a computer gaming magazine or the sandwich that I buy while waiting in endless airports and train stations to travel to my next meeting). This gives us greater freedom to use higher end tooling (like Softimage XSI) and computers to really concentrate on delivering the kind of quality products that are expected by those same customers.
TG Daily: Here's a kicker... could you tell us, at the end, what was the cost of development of PCMark® Vantage and 3DMark® Vantage, just to get the feel of the actual cost that Futuremark has to eat in order to be able to produce these titles?
Oliver: The following numbers are approximate (could be even more) - PCMark® Vantage: 1M Euro (US$1.5 Million) while 3DMark® Vantage had a budget of around 3M Euro (US$4.5 Million). This includes the cost of the team of over 30 top flight engineers and artists working for over two years on each of the benchmarks, building new engines and art from scratch as well as a highly skilled technical web team working day and night on the Online Results Browser (ORB) to be able to answer the question of how the our benchmarkers fit within the community of 20 Million results. On top of that, it includes workstations and professional external server services, multiple software licenses, travel to our many partners and conferences to learn the latest techniques, offices and the myriad of things that are required to create a breathtaking product that is both technically correct and beautiful at the same time.
TG Daily: Thank you for your time.
Oliver: Thanks Theo, I appreciate the questions and Futuremark looks forward to doing another interview with you. Also, congratulations on the new spot at TG Daily.
And in the end...
You could see that expansion of Futuremark is nowhere near being over. After launching a gaming website, and a gaming development team, only time will tell what is Futuremark's next move. Game engines used in 3DMarkVantage will be a good base for future development of original IP content from FGS.
In a way, with foundation of FGS, Futuremark makes a full circle. Company started in Finland together with Remedy (who still own a part of the company), and from 3DMarks that utilized Max Payne's Max-FX engine - we have come to the benchmark developer becoming a games developer.
While Oliver did not want to go into details, it is more than obvious that upcoming Games Developer Conference in San Francisco (Feb 18th-22nd) is going to shed some more light on plans from this very interesting company.


http://www.tomshardware.com/2008/02/...s_to_tg_daily/

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Business leaders, developers, and fans of the Python open source programming language used by Google, Industrial Light & Magic and YouTube meet March 13 to 20, 2008 at the Crowne Plaza Chicago O’Hare Hotel for PyCon 2008. This annual community conference showcases the numerous advantages and exceptional usability of Python, which is rapidly becoming the industry standard dynamic programming language.

“We use Python throughout our infrastructure,” says Chris DiBona, Open Source Programs Manager at Google. “Making extensive use of it and other open source languages and libraries allows us to rapidly build and deploy highly scalable systems.”
PyCon 2008 crams hundreds of talks, tutorials and presentations into the week-long conference. Featured this year are three days of conference sessions, a day of tutorials, in which attendees learn firsthand from Python experts, and four days of development sprints, where participants brainstorm and collaborate on projects in person. Presenters from organizations such as Google, Lockheed Martin, Red Hat, Caltech, UC Berkeley, and Oxford University will give talks on a wide variety of topics ranging from programming Python for the One Laptop Per Child project to Python use in games such as Counterstrike. Other notable sessions discuss Microsoft’s open source implementation of Python for the .NET Framework, Python 3000, scripting for the Microsoft Office system, and Jython, an implementation of Python on the Java platform that brings dynamic language features to the Java virtual machine.
“Python is consistently the ‘glue’ that brings White Oak custom software solutions together,” says Alan Broder, President of White Oak Technologies. “Our business has grown by leveraging the power of dynamic languages and open source solutions. Python is a standard part of our toolbox for a variety of purposes, including data analysis, text processing, cluster process control, web applications, rapid prototyping and system administration.”
Python has recently been in the spotlight as the engine behind some of the most recognizable sites on the Internet.
“Python has been critical in allowing us to develop and scale the YouTube site efficiently,” says Cuong Do, engineering manager for YouTube. “There have been many cases where urgent issues were resolved through a few lines of carefully written Python code.”
Python’s use by news organizations like the New York Times, by movie makers such as Disney and Industrial Light & Magic, and by game manufacturers like Valve puts Python in front of millions of people on a daily basis. In the scientific world, the use of Python by NASA, the Lawrence Berkeley National Laboratories, and AstraZeneca illustrates the practical relevance of Python to the world’s leading scientific centers. Activities at PyCon will show why Python was selected as the “Programming Language of 2007” by the TIOBE Index, a measurement of language popularity across industries.
“Microsoft is excited to support the industry standard Python language on the .NET Framework and in Silverlight,” says Dave Mendlen, director of Developer Marketing in the Developer Division at Microsoft Corp. “Dynamic languages are of growing importance to developers, and we are glad to provide comprehensive support for these languages, and particularly Python, on the Microsoft platform.”
“We chose Python because it combines structure and ease; developers love it and it’s accessible for administrators,” says Erik Dahl, Co-Founder and CTO of Zenoss. “The end result is that our product evolves quickly, it’s easy to maintain and people like working with it.”
Due to its versatility and ease of use, many organizations are turning to Python in order to write quality software in an efficient and timely manner.
“The role of the Python language for Enthought clients is evolving from a ‘useful tool’ into a critical framework at the center of their technology strategy,” says Travis Vaught, CFO of Enthought, Inc. “Scientists increasingly see Python as the best way to do numerical computing with an extensible framework.”
Some of the leading technical organizations are proud to sponsor PyCon 2008. Google and White Oak Technologies are sponsoring at the Diamond level and Enthought, Microsoft, and Zenoss at the Platinum level. Gold sponsors include Accense Technologies, ITA Software, Leapfrog Online, Predictix, Resolver Systems, and Wingware. Activestate, Canonical, Fivedash, Imaginary Landscape, Nokia, Nuance Communications, Inc., O’Reilly, PSC Consulting, Symbian, Tummy.com, and ZeOmega are Silver sponsors. Chicago-area sponsors consist of Leapfrog Online and PSC Consulting.
Early bird registration is available through February 20, 2008. Admission prices are $400 for corporate, $220 for standard, $125 for students, and $60 for a tutorial-only pass. Regular registration up to March 7, 2008 costs $500 for corporate, $300 for standard, $180 for students, and $80 for a tutorial-only pass. At the door, the cost rises to $600 for a corporate pass, $400 for standard, $250 for students, and $100 for tutorial-only passes.

For more information or to register for this event, please visit http://us.pycon.org.

About White Oak Technologies
White Oak Technologies, Inc. (WOTI) provides the next generation of solutions to massive, information-intensive, strategic intelligence challenges. WOTI’s industry leading WAREMAN® software has entity-resolved one of the worlds largest databases. WOTI is also a premier provider of advanced custom software solutions, and uses Python as a primary programming language for solving many development problems. As a past sponsor of PyCon, WOTI is honored to further support the Python community through PyCon 2008. For more information, visit www.woti.com.
About Enthought
Enthought is a privately held scientific computing company based in Austin, TX. Founded in 2001, we have built a business around providing custom applications using the Python programming language. Enthought fosters the development of the SciPy scientific library and, as a matter of practice, releases well over half of all code we write as open source (code.enthought.com). We work on extremely interesting problems in the fields of Geophysics, Finance, Electromagnetics and Fluid Dynamics–all in a fun environment full of extremely bright people. This spring we are offering an Enterprise-class distribution of the Python language (Enthought Python Distribution), which includes many scientific and application-building packages in one bundle. For more information, visit www.enthought.com.
About Zenoss
Zenoss Inc. delivers open source IT management solutions to organizations across the globe. Flagship product Zenoss Core is a complete network monitoring and systems management platform that discovers networked IT resources, monitors them for performance and availability, and tracks changes through a configuration management database (CMDB). Through our integrated, model-driven product and by taking a new approach to management software that combines the benefits of open source with the best aspects of commercial development, we offer an alternative to large proprietary software vendors. For more information, visit www.zenoss.com.
About PyCon
Presented by the Python Software Foundation, the world’s largest Python conference brings together a diverse group of developers, enthusiasts, and organizations to explore new challenges, launch new businesses and forge new connections within the Python community. PyCon provides attendees with the opportunity to delve into the dynamic programming language employed by well-known companies such as Google, iRobot, and YouTube. PyCon helps people learn new tools and techniques, showcase projects, and meet other Python fans.

Media Contact:

Daniel Schneider

Page One PR

Daniel {at} pageonepr(.)com

(415) 321-2346


http://press-releases.techwhack.com/16355/python/

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Multicore is a hot topic. Half of all embedded designs have multiple processors, and 10% of embedded designs have multiple cores on a single-chip. This percentage is slowly but surely increasing. In the same way that it is difficult to find single core devices on the desktop, it is only a matter of time before the same will be true in embedded systems.
As designers have begun to adopt multicore designs, much press has been given to the challenges posed to software developers. In fact, it has become quite fashionable for industry pundits to wax histrionic about the ills that must be endured by software developers who have been launched into a new hardware world without the proper software tools and ecosystem.
While many of the popular complaints are fiction, multicore software development does, in fact, pose some serious challenges. In this article, we will try to separate fact from fiction as we discuss a few of the key issues on the table today.
1. Refactoring embedded software to achieve concurrency is major challenge.
FICTION: It turns out that most embedded systems are already quite heavily multithreaded. It is common for embedded developers to employ real-time operating systems, and every RTOS in the world has some form of threading primitive. Embedded designers use threads as a method to simplify the management of the independent functions in the system.
On a unicore system, threads are logically concurrent, with the operating system applying core processing power to each thread in turn. On a multicore processor, these threads are naturally and truly concurrent, usually with no change in the software required (assuming a symmetic multiprocessor-capable RTOS).
Furthermore, as embedded systems have grown in complexity, adding a variety of connectivity and multimedia functions, components map naturally to threads. If the device embeds a web server, this web server uses one or more threads to serve connection requests. If the device has a file system, files are served by a number of file server threads.
Audio frameworks run as threads. CORBA and other connectivity solutions use threads. As systems designers pile on more and more applications and middleware, the number of threads increases, enabling the system to take immediate advantage of additional cores.
Of course, not all systems make optimal use of all the hardware cores. Designers may indeed want to increase concurrency by refactoring the code.
2. When refactoring software, maximize threads while minimizing processes.
FICTION: There are many ways to unlock concurrency, but coarse grained parallelism (decomposing software into large sized pieces that are mapped to threads and/or processes) is arguably the most ubiquitous, portable, and effective.
Yet when deciding whether to map a new component to a thread (sharing memory space with other threads) or a process, most designers opt for the poorer choice of threads. In fact, until recently, many embedded systems were characterized by large numbers of threads, all sharing the same memory space.
The reason for this can be attributed to the fact that the most popular RTOSes used in the 80s and early 90s did not support memory protection. Developers became accustomed to threads, and their legacy code lives on.
Of course, modern RTOSes today support memory protected processes. And while the cost (in terms of memory use and context switching time) of a process may be a bit higher than a thread, that cost has reached the threshold of negligibility with today's fast processor cores and memory architectures.
In fact, designers should strive for a 1 to 1 ratio between threads and processes. In other words, each memory protected component should have only a single thread of execution. Of course it will not always be possible to reach this ideal, but designers should strive to minimize threads in each component, particularly in new code.
Whenever possible, each component should be owned by a single developer, with clear, well-defined, message-based interfaces between components. This component management philosophy minimizes unforeseen interactions and some of the nastier multithreading problems that arise when software uses many threads, synchronized with mutexes and other error-prone constructs. Managing multithreaded components is simply more difficult, even with the best visualization and thread-aware debugging tools.
Regardless of whether threads or processes are used, an SMP-capable operating system will automatically schedule the components onto the available cores. It is this automatic load balancing that is one of the most important efficiencies realized by moving to a multicore platform.
3. The industry is suffering from a lack of multicore standardization.
FACT: A common, and valid, complaint. Multicore software needs the boost of pervasive standards. Sadly, the industry is suffering from a lack of standards in key areas. And where standards do exist, they are hobbled by politics. Open standards are important for many areas of the multicore software ecosystem. We'll cover just a few of the more visible ones: multithreading, interprocess communication, and data plane accelerators.
Multithreading: This area is actually one of the better; I would grade the industry with a B+ here. The reason is POSIX. POSIX is a collection of open standard APIs specified by the IEEE for operating system services. POSIX threads, or Pthreads, is the part of the standard that deals with multithreading.
The Pthread APIs provide interfaces for run control of threads, synchronization primitives, and IPC mechanisms. While other multithreading standards exist, Pthreads is the most generic, widely applicable standard. POSIX also provides primitives for managing protected processes.
Pthreads and processes are supported by Linux, UNIX, and a wide range of embedded operating systems such as INTEGRITY, LynxOS, and QNX. Even Windows supports a POSIX interface. Due to the ubiquity of POSIX, there exists a large base of application code that can be reused for embedded designs. Another strong advantage of POSIX is that independent conformance validation is available from the Open Group. The list of POSIX implementations that have been certified conformant to the latest POSIX specification can be found at PosixCertified.
By programming to the POSIX API, developers can write multithreaded applications that can be ported to any multicore platform running a POSIX conformant operating system. POSIX conformance is a requirement for any operating system that expects to be used widely in multicore systems.
Of course, POSIX is not the only standards effort for multithreading. Multithreading is built into some programming languages, such as Java and Ada. OpenMP allows developers to add parallelizing directives into C and C++ code. None of these other standards, however, has the widespread applicability, pedigree, and acceptance of POSIX.
POSIX itself needs some improvements for multicore. For example, while processes are part of the standard, scheduling primitives are thread-centric. As systems grow in complexity, it is desirable to schedule processes independently of threads. A designer may inherit large components, each with numerous constituent threads.
The designer should not need to understand the number or priority of threads within a component. Rather, the designer needs to be able to assign an allocation of CPU time to the component as a whole. Within the component, the normal thread scheduling can be used.
While some modern RTOSes provide this type of hierarchical scheduling capability, the distinction between threads and processes from a scheduling perspective is currently absent from the POSIX standard.
Core affinity is another concept lacking in POSIX. Core affinity is a performance feature found in most SMP-capable operating systems. When a thread migrates from one core to another, the cache locality of the thread's code and data is lost and must be reloaded on the new core.
When a thread needs to run (e.g. it is the highest priority runnable thread), and more than one core is available, the SMP operating system must intelligently choose which core to use.
The operating system usually keeps track of a thread's natural affinity. The natural affinity of a thread is defined as the core on which the thread last executed. By assigning threads to the cores that match their natural affinity, migrations and cache misses are minimized, and the embedded software will realize superior performance and power efficiency.
The other form of affinity is user-defined, and this is where the need for an API standard arises. To see where user-defined affinity is useful, consider the following example.
The SMP operating system typically provides the ability to map interrupts to specific cores. Inefficiency arises when an interrupt fires on one core, but the operating system schedules a thread to perform handling of the interrupt on a different core.
The first core must use an interprocessor interrupt (IPI) to inform the second core of the scheduling event and preempt whatever was running. Latency as well as overall system efficiency may be increased by forcefully binding the thread to the first core.
Another scenario involves assigning multiple threads cooperating to fulfill a particular job (e.g. using shared data structures). Cooperating threads can be assigned the same core affinity to minimize IPIs and maximize cache utilization.
The SMP operating system typically provides a system call to enable software to assign core affinity in this manner. POSIX, however, does not yet have a standardized API for this.
Interprocess Communication: My grade for IPC standards is a D. Message passing has long been a mechanism used to implement parallel computing, mainly because the multicomputers used historically to host massively parallel scientific computations lack a shared memory subsystem.
Rather, data for parallel computations are sent to the parallel cores using IPC, with the same IPC serving as a synchronization mechanism. Although the target applications may differ from their scientific brethren, multicore embedded systems often require IPC to achieve parallelism.
IPC comes in many flavors. In the scientific community, MPI (Message Passing Interface) is a widely used standard. POSIX, of course, specifies a variety of mechanisms, including pipes, FIFOs, and sockets, that were designed for loosely coupled IPC.
Some IPC mechanisms strive to build in fault tolerance, a desirable feature for loosely-coupled multicore systems, since one of the major advantages of these systems is the ability to recover from single-node failures. Although IPC does not inherently provide fault tolerance, the goal is to provide the building blocks “such as automatic link down detection and retransmissions " that enable developers to build survivability into their multicore systems.
One example of an IPC that attempts to provide fault tolerance features is TIPC (Transparent Interprocess Communication). TIPC is an open source package that has been ported to multiple operating systems.
TIPC has provisions for reliable message delivery, retransmission, and communication link failover. Another standard is LINX, an open sourced version of the Link Handler provided in Enea's OSE operating system.
Therein lies the rub: there is no consensus on IPC standards in the embedded systems industry. In fact, another IPC standard recently sprouted: the Multicore Association's CAPI; the good news is that this association has an impressive collection of big iron members (Intel, Freescale, TI, and NEC) that has the potential to foster widespread consensus. Stay tuned.
Data Plane Accelerators: Many of the heterogeneous, tightly-coupled multicore architectures involve the marriage of a general purpose processor (GPP) and one or more application-specific co-processors or accelerators.
In fact, this is arguably the most common multicore architecture, since many embedded designs are powered by custom ASICs consisting of a GPP and some sort of custom application-specific compute engine.
Texas Instrument's OMAP and DaVinci product lines include examples of such a multicore architecture. One flavor of Davinci marries an ARM core with a TI DSP and an additional video processing subsystem. Network processors such as the Intel IXP are another example, linking an Xscale GPP with network processing elements.
Unfortunately, due to the application-specific nature of these co-processors, there is usually no generic API upon which developers can rely. For example, TI provides a proprietary communications library, BiosLink, which must be used to communicate with the TI kernel running on the DSP.
TI also provides libraries for using the video acceleration capabilities on some DaVinci processors. Therefore, the operating system vendor must provide a port of these APIs in order for developers to make reasonable use of the part. And, of course, Bioslink does not run on non-TI devices.
Inasmuch as the offload engines provide a similar function, standardized APIs should be developed and used. For example, it is conceivable that the various vendors of network processors could standardize some of the APIs used to manage packet traffic. Sadly, like IPC, there is very little consensus in the area of heterogeneous intercore communications for software developers. Grade: C-.
4. Multicore debugging tools are lagging.
FICTION: This is another one of those mythical concerns. Although there are certainly a number of IDEs that have failed to adapt to the multicore evolution, leading IDEs have been focusing multicore support for a long time. Let's take a look at the modern multicore debugging toolbox.
On-Chip Debugging: Tightly-coupled multicore processors often provide a single on-chip debug port (e.g. JTAG) that enables a host debugger, connected with a hardware probe device, to debug multiple cores simultaneously. With this capability, developers can perform low level, synchronized run control of the multiple cores. Board bring-up and device driver development are two common uses of this type of solution.
For efficient use of this multicore hardware facility, the development tool must enable the developer to visualize all the cores of the system and choose any combination of the cores to debug, each optionally in its own window. At the same time, the tool must provide controls for synchronized running and halting of the debugged cores.
The Probe advanced hardware debug device and the MULTI IDE are one example of a development tool system that meets these requirements. The Probe's multicore debugging features were launched in 2001. MULTI, launched in the early 90s, was named in part for its ability to debug multiple processing elements simultaneously and elegantly.
Run-mode debugging is useful for both tightly and loosely-coupled multicore systems, and for heterogeneous as well as homogeneous systems. With run-mode debugging, the cores are never stopped. Rather, the debugger controls application threads using a communications channel (usually Ethernet) between the host PC and a target-resident debug agent.
For efficient use of this facility, the operating system must provide an integrated debug agent (and the associated communications device drivers) that is operating system aware and provides flexible options for interrogating the system.
For example, the Integrity operating system comes with a powerful debug agent that communicates with the MULTI debugger, providing the capability to debug any combination of user threads on any core, regardless of the homogeneity of the core architecture.
The user can set specialized breakpoints that enable user-defined groups of threads to be halted when another thread hits the breakpoint. Some classes of bugs require this fine-grained level of control.
To be able to halt threads on a core separate from the core running the thread that hits the breakpoint, the operating system must handle all the behind-the-scenes communication that informs the appropriate core, with minimal latency, of the event.
Multicore Event Analyzers: Many operating system vendors provide an event analysis tool. A target-resident agent logs important operating system level events, such as service calls, interrupts, context-switches, and user-defined events.
The tool uploads this event log (either during execution or post-mortem), and displays the events in a timeline. The tool allows the user to zoom, select specific events for further information, generate execution statistical reports, and other functions.
The event analyzer is an indispensable tool for developers of multicore software because it makes it easy to understand system behavior and locate performance bottlenecks, livelocks, or other problems.
The event analyzer must be able to show events for all threads on all the cores, with the event streams synchronized to the same time scale. The tool must be able to display IPC between the cores. EventAnalyzer product is one example of a tool that meets these requirements.
Multicore trace is another emerging behavioral analysis capability. With on-chip trace (available on a growing number of multicore processors), the behavior of multiple cores can be recorded and synchronized.
In order to take advantage of multicore trace, the development toolset must be multicore trace aware. This means that the tools must be capable of visualizing multiple execution streams so that developers can easily replay the execution of any combination of cores and determine what each core was doing at any particular time.
The TimeMachine suite is an example of a tool that takes these trace streams and provides analysis tools and backwards-in-time debugging. These tools not only make some of the most insidious multicore bugs easy to find, but they are also critical for non-intrusive performance analysis.
The aforementioned tools, and a number of others, make up some of the mature, effective technologies available in the multicore developer's arsenal. Multicore software enablement has become a controversial topic. While there are significant challenges in architecture, design, and standardization strategies, multicore developers can meet the evolving hardware landscape with confidence.

David N. Kleidermacher, Green Hills Software
David Kleidermacher is chief technology officer at Green Hills Software where he has been designing compilers, software development environments, and real-time operating systems for the past 16 years. David frequently publishes articles in trade journals and presents papers at conferences on topics relating to embedded systems. He holds a BS in computer science from Cornell University, and can be reached at davek@ghs.com.


http://www.videsignline.com/GLOBAL/e...6106197&pgno=1

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Microsoft researchers are hoping to use "information epidemics" to distribute software patches more efficiently.

Milan Vojnović and colleagues from Microsoft Research in Cambridge, UK, want to make useful pieces of information such as software updates behave more like computer worms: spreading between computers instead of being downloaded from central servers.The research may also help defend against malicious types of worm, the researchers say.Software worms spread by self-replicating. After infecting one computer they probe others to find new hosts. Most existing worms randomly probe computers when looking for new hosts to infect, but that is inefficient, says Vojnović, because they waste time exploring groups or "subnets" of computers that contain few uninfected hosts.Smart strategiesVojnović's team have designed smarter strategies that can exploit the way some subnets provide richer pickings than others.The ideal approach uses prior knowledge of the way uninfected computers are spread across different subnets. A worm with that information can focus its attention on the most fruitful subnets – infecting a given proportion of a network using the smallest possible number of probes.But although prior knowledge could be available in some cases – a company distributing a patch after a previous worm attack, for example – usually such perfect information will not be available. So the researchers have also developed strategies that mean the worms can learn from experience.In the best of these, a worm starts by randomly contacting potential new hosts. After finding one, it uses a more targeted approach, contacting only other computers in the same subnet. If the worm finds plenty of uninfected hosts there, it keeps spreading in that subnet, but if not, it changes tack.Spreading the load"After it fails to reach new uninfected hosts a fixed number of times in a row, say 10, it moves on to find new groups using random sampling," explains Vojnović. This approach performs almost as efficiently as the strategies using prior knowledge.Because no central server needs to provide and coordinate all the downloads, Software patches that spread like worms could be faster and easier to distribute because no central server must bear all the load. "These strategies can minimise the amount of global traffic across the network," Vojnović says.The research has a second potential benefit. "If we understand how future worms might be capable of spreading, we can design better countermeasures," says Vojnović. For example, some of the new strategies would flatten the usual spike in overall network activity that can give away software worm attacks, but instead they would be revealed by spikes in local traffic.'Perfect worm'Chuanyi Ji at Georgia Tech, University, US, is also interested in designing a "perfect worm". As well as revealing weaknesses of networks, such a worm could rush out defensive software patches faster than an attacking worm can spread, she says.Ji has examined records of previous worm attacks, and says there is evidence that some already use similar if less refined tricks to those developed by the Microsoft team.For example, the Blaster worm preferentially tries to infect local computers, like one of Vojnović's worms. "We may see improvements to these kind of strategies appearing in future, so it is good to investigate the worst they could do," says Ji.A paper on the Microsoft research will be presented at the 27th Conference on Computer Communications (INFOCOM) in Arizona, US, in April 2008.


http://technology.newscientist.com/a...are-fixes.html

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Technical announcements from flash memory supplier SanDisk say larger-capacity solid-state drives are on the way.

SanDisk 72GB solid state drive

(Credit: SanDisk)
Flash memory is gaining as a replacement for hard drives in ultra-thin, ultra-small notebooks such as the MacBook Air and Asus Eee PC. Why? Flash uses less power, generates less heat, and has faster access times than hard drives. The Air, for example, offers a 64GB flash-based SSD as an option while the Eee PC is sold standard with flash storage.
There is a big catch, though. High-capacity SSDs are expensive. Prohibitively so. The flash drive in the pricier $3,098 Air is the main culprit in the gaping $1,300 price difference with the lower-cost hard-drive model ($1,799). Update: SSDs also have limited write cycles. That is, flash drives can eventually "wear out" after hundreds of thousands of write cycles. File systems that spread the write over the device can extend the life cycle but it's still an issue.
The low power and high speed, however, make a flash drive almost irresistible for some users. A SanDisk SSD 1.8-inch drive achieves a sustained read rate of 66MB/sec and a random read rate of over 7,000 inputs/outputs per second for a 512-byte transfer, many times the speed of a hard drive--which must move an arm across a spinning platter to find data, the so-called seek time of a hard drive.
SanDisk will not discuss future pricing but as larger-capacity SSDs hit the market, prices are certain to fall. And eventually these will be steep price drops. For example, an 8GB SanDisk flash card now sells for about $80 at resellers. A few years ago consumers would have paid this much (or more) for a 1GB drive. (And a 1GB card was originally priced at $500 in 2004!)
SanDisk and Toshiba will start making flash memory on a new 43-nanometer manufacturing process that will result in SSDs later this year with capacities that should approach those of today's mainstream 2.5-inch hard drives, ranging between 120GB and 160GB.
The two companies recently achieved 32-gigabit (Gb) density, according to Khandker N. Quader, SanDisk's senior vice president of flash memory design and product development. The 32Gb die combined with multilevel cell (MLC) technology--which uses multiple levels per cell to allow more bits to be stored--"doubles the SSD capacity points," Quader said in a written response to questions.
Flash based on "X3" technology is another new development, Quader said. "This is an important milestone (and) allows us to do 3bits/cell as opposed to 2bits/cell thereby providing improved manufacturing efficiency," he said. "So a combination of technology scaling (i.e., 56nm to 43nm) and the bit scaling (i.e. 2bits/cell to 3bits/cell) is extremely powerful for manufacturing efficiency and for increasing capacities of flash memories."
But there are challenges. Moving to X3 can affect performance. "One very important point to take into consideration is that X3 is not a simple memory to manage," Quader said. "This is the first generation X3. We expect this to evolve in 2008."
SanDisk has also developed a 43nm 16Gb MLC for MicroSD, according to Quader. MicroSD is a tiny flash chip used in mobile phones. The new technology will double the capacity of current 8GB MicroSD, he said.


http://blogs.cnet.com/8301-13924_1-9...l?tag=blg.orig

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After years discussing verification strategies with hundreds of ASIC designers, it finally hit me: We're at the point where designers are trying to manage billions of cycles of simulation.
Take the video chip business where H.264 and high- definition TV are hot. These chip designers need to simulate hundreds of conformance streams to make sure that the chip is ready to ship. In the wireless handheld market, firmware is key. Ultimately, the device must boot Linux and run a Java application on its LCD screen. And, designers of network routers need to stress their chips through pseudo-random traffic to benchmark key performance metrics, such as packet drop rate.
All these tasks have one thing in common: they require billions of cycles of simulation. Until a designer realizes that he or she can't manage billions of cycles like any other simulation, they hit a wall that I call the "Billion-Cycle Challenge."
The first challenge, of course, is how long it takes to simulate a billion cycles. For a design of average size, register transfer level (RTL) simulation would take in the order of 10 days. This is not practical when one line of RTL code changes and all the tests need to be rerun to make sure nothing broke. Minutes would be better, right?
The second challenge is the bandwidth required to keep a chip busy for so many cycles. Let's take the example of an HDTV chip which is handling about 3 gigabits of data in real-time. If design teams have 10 days to simulate that 1 billion cycle, the testbench only needs to provide about 10 kbits of data to the design--a reasonable number. That's why everyone tends to forget about bandwidth. If the goal is to have that simulation complete in minutes, that means feeding in the order of 200 megabits to the design. It takes a special kind of testbench to move that much data around.
The third challenge is debugging. How can designers navigate through 1 billion cycles? If even feasible, a full RTL trace in a compressed format such as fast signal database (FSDB) would occupy four terabytes of data on disk. Simply reading back that file from a fast disk would take several days. Full tracing is not the way to go, either.
As in the real estate busoiness, the answer is "location, location, location." Designers want to be able to navigate between different levels of abstraction. Embedded software is the highest level and questions that are addressed at that level include:
Has the operating system booted yet?
Is the processor stuck in an interrupt handler?
Why is the device driver not handling the data properly?
Once the designer has localized--at a high-level-- where something is going wrong, he or she can start zooming in and lower the level of abstraction. That second level is implemented by monitors, checkers and assertions that help narrow the problem down and trace its likely origin. Only when designers have exhausted the information available at those two levels would they go down to the signal level and get an RTL waveform of the interesting period of time that's been identified. The ability to navigate between those different abstraction levels, from software all the way down to hardware, is the way to avoid getting lost in those huge simulations. Only by solving those three challenges simultaneously can design teams really overcome the "Billion-Cycle Challenge."


http://www.eetimes.com/news/design/r...imes_designRSS

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Robots would allow a much higher frequency of tests
US scientists are taking the first step towards testing potentially hazardous chemicals on cells grown in a laboratory, without using live animals.

Two government agencies are looking into the merits of using high-speed automated robots to carry out tests.
The long-term goal is to reduce the cost, time and number of animals used in screening everything from pesticides to household chemicals.
The move follows calls for scientists to rely less on animal studies.
Robots would be able to carry out hundreds of thousands of chemical tests a day to identify chemicals with toxic effects.
Details were published in the journal Science and discussed at the annual meeting of the American Association for the Advancement of Science (AAAS) in Boston.
Faster and cheaper
Speaking in a live link-up, Dr Francis Collins, Director of the National Human Genome Research Institute at the National Institute of Health (NIH), said high throughput screening might provide a faster, cheaper method of testing environmental chemicals.
Could we, in fact, instead of looking at a whole animal as our first line of analysis, look at individual cells?
"Although that approach has given us valuable information, it is clearly quite expensive, it is time-consuming, it uses animals in large numbers and it doesn't always predict which chemicals will be harmful to humans."
Five-year programme
The research collaboration between the NIH and the Environmental Protection Agency (EPA) has the potential to revolutionise the way that toxic chemicals are identified, he said.
"Ultimately, what you are looking for is, does this compound do damage to cells?" said Dr Collins.
"So could we, in fact, instead of looking at a whole animal as our first line of analysis, look at individual cells from different organisms of different animals with different concentrations of the compound?"
The five-year research programme will use high-speed automated screening robots developed during the human genome project.
This will allow them to complete over 10,000 screens on cells and molecules in a single day compared with 10 to 100 studies a year on rodent models.
Long-term approach
Samples of chemicals will be dropped onto dishes containing human or animal cells grown in the laboratory.
These will then be studied for signs of toxicity using a variety of biochemical and genetic tests.
The ultimate goal is to develop non-animal based testing methods that are rigorous enough to be submitted for regulatory approval.
Currently, more than 2,000 compounds are being studied for toxicological effects on rodent and human cells.
However, scientists say it will be many years before non animal-based tests become routine, if they prove successful at all.

http://news.bbc.co.uk/2/hi/science/nature/7246108.stm

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A World 1st: Laser Blasting the Event Horizon

Never mind the Nobel Prize, there's clearly some kind of secret "most awesome sounding research" award - and a team from St Andrews are after both. They're using a laser system to simulate black holes, and that concept has actually broken the laws of incredible because you couldn't make it sound any cooler even if you added cheerleaders and Optimus Prime.

Don't panic at the phrase "tabletop black holes" - the Earth won't get sucked into a cosmological trash compacter if one of the researchers hits the wrong switch. The laser system creates a situation which parallels the event horizon of a black hole without - and this is important - actually being a gravitational singularity from which nothing has any hope of escaping.
Two laser pulses are fired down a specially constructed optical fiber. The second is much faster and should rapidly overtake the first - but it can't. In a quantum effect that would make Zeno proud, the first pulse alters the speed at which light can pass through the material (in Science-ese: the refractive index is modified via the optical Kerr effect) and so the closer the second pulse gets, the stronger the effect becomes, creating an impassable barrier - a barrier like the event horizon of a black hole.
Saying "it sounds similar so we can research that instead" might not appear to be the most rigorous method in the world, but this isn't a case of hand-waving resemblance - the mathematics of the quantum catastrophe singularity created in the fiber exactly corresponds to the spacetime singularity of a black hole, in an analogy so perfectly crafted it makes Shakespeare look like a monkey with a typewriter. The quantum catastrophe singularity is therefore an accessible research tool for what - till now - was the ultimate "you can't have one in the lab" system. Quantum catastrophe singularity is also the best phrase we've ever heard, ever, and we fully intend to use it as often as possible.
The research team, led by Professor Ulf Leonhardt, first hope to investigate Hawking radiation - proof of which would see King of Cosmology, Professor Stephen Hawking, land a Nobel prize. To which any reasonable person would respond "What? You mean he doesn't have one yet?" Apparently not - an oversight the Scottland-based team intend to rectify.
And one more time: quantum catastrophe singularity


http://www.dailygalaxy.com/my_weblog...d-1st-sim.html

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Expedition 01
Recently an international partnership led by the Directorate General of Hydrocarbons (DGH) under the Ministry of Petroleum and Natural Gas (Government of India) and the U.S. Geological Survey (USGS) released the results of the most complex and comprehensive gas hydrate field venture yet conducted. Upon the occasion of the Indian National Gas Hydrate Program Gas Hydrate Conference held February 6-8, 2008 in New Delhi, India, the leadership and participants in the Indian National Gas Hydrate Program (NGHP) Expedition 01 are pleased to release the results of the first modern, fully integrated gas hydrate research and exploration program conducted in the offshore of India.

What Are Gas Hydrates?

A gas hydrate is a crystalline solid; its building blocks consist of a
gas molecule surrounded by a cage of water molecules. Thus it is
similar to ice, except that the crystalline structure is stabilized by
the guest gas molecule within the cage of water molecules.

Gas hydrates are a naturally occurring “ice-like” combination of natural gas (usually methane) and water that have the potential to provide an immense resource of natural gas from the world’s oceans and polar regions. In 1990’s, the U.S. Geological Survey made the first systematic assessment of the volume of gas stored in natural gas hydrates. That study suggested that the amount of gas in the gas hydrate accumulations of the world greatly exceeds the volume of known conventional gas resources. However, gas hydrates represent both a scientific and technologic challenge and much remains to be learned about the geologic, engineering, and economic factors controlling the ultimate energy resource potential of gas hydrates.
The amount of natural gas contained in the world's gas hydrate accumulations is enormous, but these estimates are speculative and range over three orders of magnitude from about 2,800 to 8,000,000 trillion cubic meters of gas. By comparison, conventional natural gas accumulations (reserves and technically recoverable undiscovered resources) for the world are estimated at approximately 440 trillion cubic meters as reported in the USGS World Petroleum Assessment 2000 (http://pubs.usgs.gov/dds/dds-060/). Gas recovery from hydrates is hindered because the gas is in a solid form and because hydrates commonly occur in remote Arctic and deep marine environments. Proposed methods of gas recovery from hydrates generally deal with dissociating gas hydrates in situ by heating the reservoir beyond the temperature of gas hydrate formation, or decreasing the reservoir pressure below hydrate equilibrium. The pace of gas hydrate energy characterization and assessment projects has accelerated over the past several years. Researchers have long speculated that gas hydrates could eventually be a commercial resource yet technical and economic hurdles have historically made gas hydrate development a distant goal rather than a near-term possibility. This view began to change with the realization that this unconventional resource could be developed in conjunction with conventional gas fields.

Expedition Objectives

• GNGHP Expedition 01 was designed to study the gas hydrate occurrences both spatially and temporally off the Indian Peninsula and along the Andaman convergent margin with special emphasis on understanding the geologic and geochemical controls on the occurrence of gas hydrate in these two diverse settings. The primary goal of NGHP Expedition 01 was to conduct scientific ocean drilling/coring, logging, and analytical activities to assess the geologic occurrence, regional context, and characteristics of gas hydrate deposits along the continental margins of India in order to meet the long term goal of exploiting gas hydrates as a potential energy resource in a cost-effective and safe manner. During NGHP Expedition 01, dedicated gas hydrate coring, drilling, and downhole logging operations were conducted from 28 April, 2006 to the 19 August, 2006.
• Based on analysis of geological and geophysical data, the Expedition was planned to visit ten sites in four areas: the Kerala-Konkan Basin in the Arabian Sea – western continental shelf of India; the petroliferous Krishna-Godawari Basin and Mahanadi Basin in the Bay of Bengal – eastern continental shelf of India; and the previously unexplored Andaman Islands. The goals of the cruise were to conduct scientific drilling, well logging, coring, and shipboard scientific analyses of recovered samples from each site to provide further insight into:
• the distribution and nature of gas hydrate in marine sediments
• the geologic controls on the formation and occurrence of gas hydrate in nature
• the processes that transport gas from source to reservoir
• the effect of gas hydrate on the physical properties of the host sediments
• the microbiology and geochemistry of gas hydrate formation and dissociation
• the calibration of geophysical and other predictive tools to the observed presence and concentration of gas hydrates.

Participants
NGHP Expedition 01 was planned and managed through a collaboration between the Directorate General of Hydrocarbons (DGH) under the Ministry of Petroleum and Natural Gas (Government of India), the U.S. Geological Survey (USGS), and the Consortium for Scientific Methane Hydrate Investigations (CSMHI) led by Overseas Drilling Limited (ODL) and FUGRO McClelland Marine Geosciences (FUGRO). The platform for the drilling operation was the research drill ship JOIDES Resolution (JR), operated by ODL. Much of the drilling/coring equipment used was provided by the Integrated Ocean Drilling Program (IODP) through a loan agreement with the US National Science Foundation (NSF). Wireline pressure coring systems and supporting laboratories were provided by IODP/Texas A&M University (TAMU), FUGRO, USGS, U.S. Department of Energy (USDOE) and HYACINTH/GeoTek. Downhole logging operational and technical support was provided by Lamont-Doherty Earth Observatory (LDEO) of Columbia University.
The science team was led by Dr. Timothy Collett of the USGS, and consisted of more than 100 leading scientists and professionals representing the following organizations:

• Binghamton University Colorado School of Mines
• Directorate General for Hydrocarbons (India)
• Fugro-McClelland, Inc.
• GAIL (India) Ltd
• Geological Survey of Canada
• Geotek Ltd
• Idaho National Laboratory
• Integrated Ocean Drilling Program
• Joint Oceanographic Institutions, Inc.
• Lamont-Doherty Earth Observatory
• Ministry of Petroleum and Natural Gas (India)
• McGill University
• National Energy Technology Laboratory
• National Institute of Oceanography (India)
• National Institute of Ocean Technology (India)
• Oil and Natural Gas Corporation (India)
• Ocean Drilling Limited
• Oregon State University OIL India Ltd
• Pacific Northwest National Laboratory
• Reliance Industries Limited (India)
• Schlumberger
• Technical University of Berlin
• Texas A&M University
• University of California, San Diego
• University of Cardiff
• University of New Hampshire
• Universität Bremen
• University of Rhode Island
• U.S. Department of Energy
• U.S. Geological Survey
• U.S. National Science Foundation
• Woods Hole Oceanographic Institution

Operational Highlights
During its 113.5-day voyage, the expedition cored or drilled 39 holes at 21 sites (one site in the Kerala-Konkan Basin, 15 sites in the Krishna-Godavari Basin, four sites in the Mahanadi Basin and one site in the Andaman deep offshore areas), penetrated more than 9,250 meters of sedimentary section, and recovered nearly 2,850 meters of core. Twelve holes were logged with logging-while-drilling (LWD) tools and an additional 13 holes were wireline logged. The operational highlights of NGHP Expedition 01 included the following:

• 113.5 days of operation without any reportable injury or incident.
• Only 1% of total operation time was down time due to equipment malfunction or weather.
• Examination of 9,250 meters of sedimentary section at 39 locations within 21 sites located in four geologically-distinct settings.
• Collected LWD log data in 12 holes at 10 sites.
• Collected wireline log data at 13 sites.
• Collected vertical seismic profile data at six sites.
• Collected 494 cores, encompassing 2,850 meters of sediment, from 21 holes (78% overall recovery).
• Collected detailed shallow geochemical profiles at 13 locations.
• Established temperature gradients at 11 locations.
• Extensive sample collection to support a wide range of post-cruise analyses, including:
• Collected about 6,800 whole round core samples for examination of interstitial water geochemistry, microbiology, and other information.
• Collected more than 12,500 core subsamples for paleomagnetic, mineralogical, paleontological, and other analyses.
• Collected about 140 gas-hydrate-bearing sediment samples for storage in liquid nitrogen.
• Collected five one-meter-long gas-hydrate-bearing pressure cores for analysis of the physical and mechanical properties of gas-hydrate-bearing sediment.
• Collected 21 re-pressurized cores (nine representing sub-samples from gas-hydrate-bearing pressure cores).
• Conducted 97 deployments of advanced pressure coring devices, resulting in the collection of 49 cores that contain virtually undisturbed gas hydrate in host sediments at near in situ pressure conditions.

Scientific Findings and Impact
The NGHP Expedition 01 Initial Reports, released at the conference in New Delhi, includes a series of integrated site chapters (Sites 1-21) describing the operational history and scientific data collected during the expedition. The Initial Reports volume also includes a companion publication that contains all downhole log data collected during the expedition.
The NGHP Expedition 01 science team utilized extensive on-board lab facilities to examine and prepare preliminary reports on the physical properties, geochemistry, and sedimentology of all the data collected prior to the end of the expedition. Although the data will continue to inform gas hydrates science for years to come, the following are some key scientific highlights of the expedition to date:

• Conducted comprehensive analyses of gas-hydrate-bearing marine sediments in both passive continental margin and marine accretionary wedge settings.
• The calculated depth to the base of the methane hydrate stability zone, as derived from downhole temperature measurements, closely matches the depth of the seismic identified bottom simulating reflectors (BSRs) at most of the sites established during this expedition.
• Discovered gas hydrate in numerous complex geologic settings and collected an unprecedented number of gas hydrate cores.
• Most of the recovered gas hydrate was characterized as either pore-filling grains or particles disseminated in coarser grain sediments or as a fracture-filling material in clay dominated sediments.
• The occurrence of concentrated gas hydrate is mostly controlled by the presence of fractures and/or coarser grained (mostly sand-rich) sediments.
• Gas hydrate was found occurring in “combination reservoirs” consisting of horizontal or subhorizontal coarse grained permeable sediments (sands for the most part) and apparent vertical to subvertical fractures that provide the conduits for gas migration.
• Delineated and sampled one of the richest marine gas hydrate accumulations ever discovered (Site NGHP-01-10 in the Krishna-Godavari Basin).
• Discovered one of the thickest and deepest gas hydrate occurrences yet known (offshore of the Andaman Islands, Site NGHP-01-17) which revealed gas-hydrate-bearing volcanic ash layers as deep as 600 meters below the seafloor.
• Established the existence of a fully developed gas hydrate system in the Mahanadi Basin of the Bay of Bengal.
• Most of the gas hydrate occurrences discovered during this expedition appear to contain mostly methane which was generated by microbial processes. However, there is also evidence of a thermal origin for a portion of the gas within the hydrates of the Mahanadi Basin and the Andaman offshore area.
• Gas hydrate in the Krishna-Godavari Basin appears to be closely associated with large scale structural features, in which the flux of gas through local fracture systems, generated by the regional stress regime, controls the occurrence and distribution of gas hydrate.

Future Directions
NGHP Expedition 01 has shown that conventional sand and fractured-clay reservoirs are the primary emerging economic targets for gas hydrate production in India. Because conventional marine exploration and production technologies favor the sand-dominated gas hydrate reservoirs, investigation of sand reservoirs will likely have a higher near-term priority in the NGHP program. It is perceived that the NGHP effort will likely include future seismic studies, drilling, coring, and field production testing. It has been concluded that Site 10 represents a world class shale dominated fracture gas hydrate reservoir, worthy of further investigation. NGHP Expedition 01 also discovered significant sand and silt dominated gas hydrate reservoirs. It has been proposed that in a 2009-2010 time-frame, NGHP Expedition 02 may be constituted to drill and log several of the most promising gas hydrate sand-dominated prospects.


http://energy.usgs.gov/other/gashydrates/india.html

***

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Emotiv Systems today unveiled the EPOC, a neuroheadset that
allows users to control gameplay simply with their thoughts.
IBM said that it is looking for ways to extend the EPOC beyond
games into enterprise business markets.

Emotiv said that the EPOC is advanced enough to detect more than 30 different expressions, including immersion, excitement, meditation, tension and frustration; facial expressions such as smile, laugh, wink, crossed eyes, shock (through raised eyebrows), anger, horizontal eye movement, smirk and grimace (through clenched teeth). The device is also able to detect cognitive actions such as push, pull, lift, drop and rotate (on six different axis) as well as a "completely new category of action based on visualization, the first of which is the ability to make objects disappear."
The manufacturer is using "non-invasive" electroencephalography to monitor electrical impulse emitted by about 100 billion neurons in the brain. "Brain computer interface technology works by observing an individual's electrical brain activity and processing it so that computers can take inputs from the human brain," Emotiv said.
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As a result, games will be able to respond dynamically to player emotions, Emotiv said. The company promises that players can more easily control certain actions and expressions and manipulating objects in the game using their brains instead of a keyboard or controller. In addition to these detections, the Emotiv EPOC comes with a gyroscope, which enables the camera or cursor to be controlled by head motions.
The headset is expected to ship late this year and carry a suggested retail price of $299.
IBM apparently has jumped on Emotiv's idea already, saying that it will explore the potential of the technology into more strategic enterprise business markets and virtual worlds. Besides making these environments more "personal, intuitive, immersive and ultimately more lifelike", IBM envisions applications such as virtual training and learning, collaboration, development, design and sophisticated simulation platforms for industries such as enterprise and government.


http://www.tomshardware.com/2008/02/...set_unveiled_/

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Can scientists use the binary of biology, DNA, to
grow carbon nanotubes into more efficient circuits?
IBM thinks so.

Scientists at IBM are conducting research into arranging carbon nanotubes -- tubes of carbon atoms that can conduct electricity -- into arrays with DNA molecules. Once the nanotube array has been constructed, the laboratory-generated DNA molecules could be removed, leaving an orderly grid of nanotubes. The nanotube grid, conceivably, could function as a data-storage device or perform calculations.
"These are DNA nanostructures that are self-assembled into discrete shapes. Our goal is to use these structures as bread boards on which to assemble carbon nanotubes, silicon nanowires, quantum dots," said Greg Wallraff, an IBM scientist and a lithography and materials expert working on the project. "What we are really making are tiny DNA circuit boards that will be used to assemble other components."
The work, which builds on the ground-breaking research on "DNA origami" conducted by the California Institute of Technology's Paul Rothemund, is only in the preliminary stages. Nonetheless, a growing number of researchers believe that designer DNA could become the vehicle for turning the long-touted dream of "self-assembly" into reality.
Chips made on these procedures could also be quite small. Potentially, DNA could address, or recognise, features as small as 2nm (nanometres). Cutting-edge chips today have features that average 45nm, or 45 billionths of a metre.
"There is nothing else out there that we can do that with," said Jennifer Cha, an IBM biochemist working on getting the biological and non-biological (inorganic) molecules to interact.
Today, products get manufactured in a top-down approach, with machinery and equipment manipulating raw materials. In self-assembly, the intrinsic chemical and physical properties of molecules, along with environmental factors, coax the raw materials into complex structures. It works with snowflakes, after all.
Getting the raw materials to behave in a precise, orderly manner, however, remains a challenge, which is where DNA comes in. DNA consists of specific chemical bases (guanine and cytosine, for example) that bind and react in somewhat predictable ways with each other.
"The sequence [of base pairs in DNA] is well known," said Cha. "Most people are acknowledging that DNA and these biological scaffolds are actually quite useful to at least pattern very small systems."
How it works
In creating chip arrays, DNA assembly might work as follows: scientists would first create scaffolds of designer DNA manipulated into specific shapes. Rothemund has made DNA structures in the shapes of circles, stars and happy faces.
A pattern would then be etched into a photo-resistant surface with electron beam lithography and the combination of several interacting thin films. A solution of the designer DNA would then be poured on the patterned surface and the DNA would space themselves out according to the patterns on the substrate and the chemical and physical forces between the molecules.
The nanotubes would then be poured in. Interactions between the nanotubes and the DNA would occur until they formed the desired pattern. Single-strand DNA, along with origami, could be used in concert.
Another key part in the system revolves around peptides that can bind to the DNA and a non-biologically inspired molecule, like a nanotube.
"Building a DNA scaffold is not trivial because you need the biological system to recognise something that doesn't exist at all in biology," said Cha. "We can also use these biomechanical scaffolds to position inorganic nanomaterials. Potentially, we could also use these biomechanical systems to synthesise inorganic materials."
Although it's early, progress is being made. Researchers have published papers on how DNA can coil around nanotubes and disperse them in water. Papers detailing how DNA can arrange nanotubes will come soon. Future experiments will need to be conducted into aligning nanotubes into arrays. Other researchers in this field include Nadrian Seeman at New York University and Thomas LaBean at Duke University.
IBM will also examine ways of employing DNA to sort nanotubes, said Cha. Not all nanotubes are equal. The arrangement and relative position of carbon atoms in a nanotube, called "chirality", can change the properties of that nanotube. Chirality refers to molecules that are mirror images -- for example your hands are chiral -- even thought they are identical one is "left" while the other is "right". Chiral molecules are notoriously difficult to sort from each other, but would have different interactions with DNA depending on their chirality.
In addition some nanotubes don't conduct, even though they were made with others that do conduct. Separating conducting from non-conducting nanotubes currently requires applying an electric field or soaking them in sorting solutions.
If DNA manufacturing can become a reality, worries about the pace of progress in the computing world slowing down because of the difficulties involved in following Moore's Law would probably fade, at least for a while. Chipmakers shrink the size of the features of their chips every two years. While this improves the performance, producing smaller circuits has strained the financial and technical resources of the industry. The limits of lithography -- used to "draw" circuits -- have prompted many, including Intel co-founder Gordon Moore, to predict that the pace of progress will slow down.
By using DNA, chipmakers could phase out multi-billion fabrication facilities stocked with lithography systems, which cost tens of millions of dollars, and the other "top-down" style equipment.
Potentially, DNA techniques could allow manufacturers to produce features that are smaller than patterns that could be achieved even with the most advanced lithography systems, said Wallraff. Electron beam lithography, which is extremely difficult to use in mass manufacturing, goes down to 10nm.
"Of course, the devil is in the detail," said Wallraff. "These are self-assembly procedures and error rates -- missing features -- could be the downfall."


http://www.zdnet.com.au/news/hardwar...0.htm?feed=rss

[bbmf]

...but real battle lies ahead

Sony won the home movie DVD format war, but the consumer-electronics giant faces an even tougher battle persuading shoppers to buy Blu-ray discs in an industry which is looking to the download era.With Sony's current three-year business plan set to end on March 31, Chief Executive Howard Stringer also has to convince investors it has a new growth strategy for the maker of PlayStation game players and Bravia flat-screen televisions as it gets squeezed hard by rivals.
"The end of the format battle does not automatically guarantee a swift shift to Blu-ray," said Kazuharu Miura, an analyst at Daiwa Institute of Research.

"The big challenge is how they communicate Blu-ray's benefits to the potential users who already own DVD machines."
Toshiba called time on its rival HD DVD format this week, leaving the Sony camp free to pursue a home movie market worth up to US$24 billion a year.
But Sony has become heir to that fortune at a time when more consumers are bypassing stored movies and games altogether and downloading them.
"We believe it is highly likely that the Internet will become the mainstream method of distributing visual content, in the same way as with music," Mitsubishi UFJ Securities analyst Yukihiko Shimada said in a research note.
Industry specialists say, however, it will be quite some time before telecommunications infrastructure becomes strong enough to allow people to download high-resolution feature-length movies with reasonable time and costs.
Sony does have its eye on this market too. Stringer said in December he sees its PlayStation 3-based online content distribution service, the PlayStation Network, as a key growth driver for the Japanese company.
Both Microsoft and Apple Inc already offer downloading services for non-game entertainment content such as TV programmes. Sony's PlayStation Network now mainly offers videogame software and game-related promotional video clips.
GAME PAUSED
Sony announced that its PlayStation 3 game console would be equipped with a Blu-ray player more than two years ahead of the actual console launch in a bid to win support for the format from hardware as well as software providers.
But Sony is paying the price of seeding the market with future high-definition movie buyers. The cost of the console's Blu-ray function and its high performance chip forced Sony to take a loss on each console sold even though it was initially priced twice as high as rival Nintendo Co Ltd's Wii.
Sony's game division is expected to post an operating loss in excess of more than US$900 million for the full year, making it together and the flat TV business Sony's two biggest earnings drags.
"By eliminating losses in these two operations next business year, Sony's profit could get a boost of some 150 billion yen," Credit Suisse analyst Koya Tabata said.
Sony expects PS3 manufacturing costs to fall below selling prices in the second half of the business year starting in April.
It also hopes that new titles, such as Konami Corp's "Metal Gear Solid 4: Guns of the Patriots", due to be launched this spring, will drive demand for PS3 consoles and help it catch up with Nintendo's Wii and Microsoft's Xbox 360.
But support for the PS3 from game software publishers may not be as solid as that extended to the Blu-ray format from electronics makers and Hollywood film studios.
Nintendo said in October Capcom would develop the latest version of its blockbuster "Monster Hunter" action game for the Wii. The game had previously been developed for Sony machines, and the switch fed speculation that support for PlayStation franchise may be slipping.
CLEAR VISION
Competition is no less fierce in liquid crystal display TVs.
Sony beat Samsung Electronics to become the top LCD TV supplier in the key North American market in the last quarter of 2007, but Sony's market share was just 0.5 percentage point above Samsung's, according to research firm DisplaySearch.
Sharp is building the world's largest LCD plant, while Panasonic maker Matsushita Electric Industrial is planning a US$2.8 billion panel factory, all aiming to boost their share of the fast growing market.
"This is one area where none in the industry is doing particularly well in terms of profitability. I see no specific solution for Sony. They just have to boost sales and achieve economies of scale," Daiwa's Miura said.
Sony now expects an operating profit margin of 4.6 percent this business year, missing its business plan target of 5 percent.
"What Sony management has been required to do over the past few years is bring the firm back to a decent level of profitability. Whether it's 4.6 percent or 5 percent, the mission is completed," Nomura Securities analyst Eiichi Katayama said.
"The point is if it can offer us a clear vision for the next three years and beyond ... Yes, it needs to turn loss-making businesses profitable. But how the conglomerate will transform itself is far more important an issue."


http://www.itnews.com.au/News/NewsSt...px?story=70593

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For decades, some of engineering’s best minds have focused their thinking skills on how to create thinking machines — computers capable of emulating human intelligence.
Why should you reverse-engineer the brain?
While some of thinking machines have mastered specific narrow skills — playing chess, for instance — general-purpose artificial intelligence (AI) has remained elusive.
Part of the problem, some experts now believe, is that artificial brains have been designed without much attention to real ones. Pioneers of artificial intelligence approached thinking the way that aeronautical engineers approached flying without much learning from birds. It has turned out, though, that the secrets about how living brains work may offer the best guide to engineering the artificial variety. Discovering those secrets by reverse-engineering the brain promises enormous opportunities for reproducing intelligence the way assembly lines spit out cars or computers.
Figuring out how the brain works will offer rewards beyond building smarter computers. Advances gained from studying the brain may in return pay dividends for the brain itself. Understanding its methods will enable engineers to simulate its activities, leading to deeper insights about how and why the brain works and fails. Such simulations will offer more precise methods for testing potential biotechnology solutions to brain disorders, such as drugs or neural implants. Neurological disorders may someday be circumvented by technological innovations that allow wiring of new materials into our bodies to do the jobs of lost or damaged nerve cells. Implanted electronic devices could help victims of dementia to remember, blind people to see, and crippled people to walk.
Sophisticated computer simulations could also be used in many other applications. Simulating the interactions of proteins in cells would be a novel way of designing and testing drugs, for instance. And simulation capacity will be helpful beyond biology, perhaps in forecasting the impact of earthquakes in ways that would help guide evacuation and recovery plans.
Much of this power to simulate reality effectively will come from increased computing capability rooted in the reverse-engineering of the brain. Learning from how the brain itself learns, researchers will likely improve knowledge of how to design computing devices that process multiple streams of information in parallel, rather than the one-step-at-a-time approach of the basic PC. Another feature of real brains is the vast connectivity of nerve cells, the biological equivalent of computer signaling switches. While nerve cells typically form tens of thousands of connections with their neighbors, traditional computer switches typically possess only two or three. AI systems attempting to replicate human abilities, such as vision, are now being developed with more, and more complex, connections.
What are the applications for this information?
Already, some applications using artificial intelligence have benefited from simulations based on brain reverse-engineering. Examples include AI algorithms used in speech recognition and in machine vision systems in automated factories. More advanced AI software should in the future be able to guide devices that can enter the body to perform medical diagnoses and treatments.
Of potentially even greater impact on human health and well-being is the use of new AI insights for repairing broken brains. Damage from injury or disease to the hippocampus, a brain structure important for learning and memory, can disrupt the proper electrical signaling between nerve cells that is needed for forming and recalling memories. With knowledge of the proper signaling patterns in healthy brains, engineers have begun to design computer chips that mimic the brain’s own communication skills. Such chips could be useful in cases where healthy brain tissue is starved for information because of the barrier imposed by damaged tissue. In principle, signals from the healthy tissue could be recorded by an implantable chip, which would then generate new signals to bypass the damage. Such an electronic alternate signaling route could help restore normal memory skills to an impaired brain that otherwise could not form them.
“Neural prostheses” have already been put to use in the form of cochlear implants to treat hearing loss and stimulating electrodes to treat Parkinson’s disease. Progress has also been made in developing “artificial retinas,” light-sensitive chips that could help restore vision.
Even more ambitious programs are underway for systems to control artificial limbs. Engineers envision computerized implants capable of receiving the signals from thousands of the brain’s nerve cells and then wirelessly transmitting that information to an interface device that would decode the brain’s intentions. The interface could then send signals to an artificial limb, or even directly to nerves and muscles, giving directions for implementing the desired movements.
Other research has explored, with some success, implants that could literally read the thoughts of immobilized patients and signal an external computer, giving people unable to speak or even move a way to communicate with the outside world.
What is needed to reverse-engineer the brain?
The progress so far is impressive. But to fully realize the brain’s potential to teach us how to make machines learn and think, further advances are needed in the technology for understanding the brain in the first place. Modern noninvasive methods for simultaneously measuring the activity of many brain cells have provided a major boost in that direction, but details of the brain’s secret communication code remain to be deciphered. Nerve cells communicate by firing electrical pulses that release small molecules called neurotransmitters, chemical messengers that hop from one nerve cell to a neighbor, inducing the neighbor to fire a signal of its own (or, in some cases, inhibiting the neighbor from sending signals). Because each nerve cell receives messages from tens of thousands of others, and circuits of nerve cells link up in complex networks, it is extremely difficult to completely trace the signaling pathways.
Furthermore, the code itself is complex — nerve cells fire at different rates, depending on the sum of incoming messages. Sometimes the signaling is generated in rapid-fire bursts; sometimes it is more leisurely. And much of mental function seems based on the firing of multiple nerve cells around the brain in synchrony. Teasing out and analyzing all the complexities of nerve cell signals, their dynamics, pathways, and feedback loops, presents a major challenge.
Today’s computers have electronic logic gates that are either on or off, but if engineers could replicate neurons’ ability to assume various levels of excitation, they could create much more powerful computing machines. Success toward fully understanding brain activity will, in any case, open new avenues for deeper understanding of the basis for intelligence and even consciousness, no doubt providing engineers with insight into even grander accomplishments for enhancing the joy of living.


http://www.uncommondescent.com/intel...and-challenge/

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First ``Full Field'' EUV Test Chip from AMD, IBM Alliance Demonstrates Integration Capability of EUV Lithography into Standard Fab Process Flow.

Working together with its research partner, IBM, announced it has produced a working test chip utilizing Extreme Ultra-Violet (EUV) lithography for the critical first layer of metal connections across the entire chip. Previous projects utilizing EUV to produce working chip components were only “narrow field”, covering just a very small portion of the design. The work of AMD, IBM, and their partners at the UAlbany NanoCollege’s Albany NanoTech Complex, will be presented by Dr. Bruno La Fontaine of AMD at the premier lithography conference in the industry on Tuesday. The paper will show successful integration of “full-field” EUV lithography into the fabrication process across an entire 22 mm x 33 mm AMD 45 nm node test chip.
“This important demonstration of EUV lithography’s potential to be used in semiconductor manufacturing in the coming years is encouraging to all of us in the industry that benefit from chip feature sizes shrinking over time,” said La Fontaine. “Although there is still a lot of work to be done before the industry can use EUV lithography in high volume production, AMD has shown it can be integrated successfully in a semiconductor fabrication flow to produce the first layer of metal interconnects across a full chip.”
“Collaborative research is essential to enabling advancements in semiconductor research,” said David Medeiros, manager of Patterning Research for IBM in Albany, NY. “Our partnerships at the Albany facility are allowing for assessment of the various aspects of the EUV infrastructure in an integrated way, and will be the true test of this technology’s readiness for manufacturing.”
Lithography is how highly complex chip designs with millions of transistors, like microprocessors, are transferred onto the silicon wafer for the many layers required to build a chip. As chip designers continue to add functions and increase the performance of their products, making the transistors smaller and smaller makes more transistors available within a given area. How small transistors and the metal lines that connect them can be made is directly related to the wavelength of light that is used to project a chip design onto a wafer. EUV lithography uses a wavelength of 13.5 nm, significantly shorter than today’s 193 nm lithography techniques, allowing the traditional scaling of chip feature sizes to continue.
The AMD test chip first went through processing at AMD’s Fab 36 in Dresden, Germany, using 193 nm immersion lithography, the most advanced lithography tools in high volume production today. The test chip wafers were then shipped to IBM’s Research Facility at the College of Nanoscale Science and Engineering (CNSE) in Albany, New York where AMD, IBM and their partners used an ASML EUV lithography scanner installed in Albany through a partnership with ASML, IBM and CNSE, to pattern the first layer of metal interconnects between the transistors built in Germany. After patterning, etch and metal deposition processes, among others, the EUV device structures underwent electrical testing at AMD, with transistors showing characteristics very consistent with those of test chips built using only 193 nm immersion lithography. These wafers will receive additional metal interconnect layers using standard Fab processing so that large memory arrays can also be tested.
The next step in proving viability of the EUV lithography for production will be to apply it not only to metal interconnects but to all critical layers to show an entire working microprocessor can be made utilizing EUV lithography. EUV lithography will need to be fully qualified for production prior to 2016, when the 22 nm half-pitch node on the International Technology Roadmap for Semiconductors is expected to be reached.


http://www.amdzone.com/index.php/new...-ultra-violet-

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A new form of carbon being pioneered by Walter de Heer of Georgia Tech could lead to speedy, compact computer processors.

The remarkable increases in computer speed over the last few decades could be approaching an end, in part because silicon is reaching its physical limits. But this past December, in a small Washington, DC, conference room packed to overflowing with an audience drawn largely from the semiconductor industry, Georgia Tech physic�*s professor Walter de Heer described his latest work on a surprising alternative to silicon that could be far faster. The material: graphene, a seemingly unimpressive substance found in ordinary pencil lead.
Theoretical models had previously predicted that graphene, a form of carbon consisting of layers one atom thick, could be made into transistors more than a hundred times as fast as today's silicon transistors. In his talk, de Heer reported making arrays of hundreds of graphene transistors on a single chip. Though the transistors still fall far short of the material's ultimate promise, the arrays, which were fabricated in collaboration with MIT's Lincoln Laboratory, offer strong evidence that graphene could be practical for future generations of electronics.
video link>>>

Today's silicon-based computer processors can perform only a certain number of operations per second without overheating. But electrons move through graphene with almost no resistance, generating little heat. What's more, graphene is itself a good thermal conductor, allowing heat to dissipate quickly. Because of these and other factors, graphene-based electronics could operate at much higher speeds. "There's an ultimate limit to the speed of silicon--you can only go so far, and you cannot increase its speed any more," de Heer says. Right now silicon is stuck in the gigahertz range. But with graphene, de Heer says, "I believe we can do a terahertz--a factor of a thousand over a gigahertz. And if we can go beyond, it will be very interesting."
Besides making computers faster, graphene electronics could be useful for communications and imaging technolo�*gies that require ultrafast transistors. Indeed, graphene is likely to find its first use in high-frequency applications such as terahertz-wave imaging, which can be used to detect hidden weapons. And speed isn't graphene's only advantage. Silicon can't be carved into pieces smaller than about 10 nanometers without losing its attractive electronic properties. But the basic physics of graphene remain the same--and in some ways its electronic properties actually improve--in pieces smaller than a single nanometer.
Interest in graphene was sparked by research into carbon nanotubes as potential successors to silicon. Carbon nanotubes, which are essentially sheets of graphene rolled up into cylinders, also have excellent electronic properties that could lead to ultrahigh-�*performance electronics. But nanotubes have to be carefully sorted and positioned in order to produce complex circuits, and good ways to do this haven't been developed. �*Graphene is far easier to work with.
In fact, the devices that de Heer announced in December were carved into graphene using techniques very much like those used to manufacture silicon chips today. "That's why industry people are looking at what we're doing," he says. "We can pattern graphene using basically the same methods we pattern silicon with. It doesn't look like a science project. It looks like technology to them."
Graphene hasn't always looked like a promising electronic material. For one thing, it doesn't naturally exhibit the type of switching behavior required for computing. Semiconductors such as silicon can conduct electrons in one state, but they can also be switched to a state of very low conductivity, where they're essentially turned off. By contrast, graphene's conductivity can be changed slightly, but it can't be turned off. That's okay in certain applications, such as high-frequency transistors for imaging and communications. But such transistors would be too inefficient for use in computer processors.
In 2001, however, de Heer used a computer model to show that if graphene could be fashioned into very narrow ribbons, it would begin to behave like a semiconductor. (Other researchers, he learned later, had already made similar observations.) In practice, de Heer has not yet been able to fabricate graphene ribbons narrow enough to behave as predicted. But two other methods have been shown to have similar promise: chemically modifying graphene and putting a layer of graphene on top of certain other substrates. In his presentation in Washington, de Heer described how modifying graphene ribbons with oxygen can induce semiconducting behavior. Combining these different techniques, he believes, could produce the switching behavior needed for transistors in computer processors.
Meanwhile, the promise of graphene electronics has caught the semiconductor industry's attention. Hewlett-�*Packard, IBM, and Intel.


http://www.technologyreview.com/read...08&id=20242&a=